From: Noam Camus <noamc@ezchip.com>
To: Thomas Gleixner <tglx@linutronix.de>
CC: "linux-snps-arc@lists.infradead.org" 
	<linux-snps-arc@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Tal Zilcer <talz@ezchip.com>, Gil Fruchter <gilf@ezchip.com>,
        Chris Metcalf <cmetcalf@ezchip.com>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: [PATCH v2 04/19] irqchip: add nps Internal and external irqchips
Thread-Topic: [PATCH v2 04/19] irqchip: add nps Internal and external irqchips
Thread-Index: AQHRGUrEmVVkCk4S7Ei6+c/JT/0u0Z6QbwOAgACYuVE=
Date: Sat, 7 Nov 2015 20:52:10 +0000
Message-ID: <DB5PR02MB1141A8FD2BC4427FBAF2C286D6170@DB5PR02MB1141.eurprd02.prod.outlook.com>
References: <1446297327-16298-1-git-send-email-noamc@ezchip.com>
 <1446893557-29748-5-git-send-email-noamc@ezchip.com>,<alpine.DEB.2.11.1511071227030.4032@nanos>
In-Reply-To: <alpine.DEB.2.11.1511071227030.4032@nanos>
Accept-Language: en-US
Content-Language: en-US
spamdiagnosticoutput: 1:23
spamdiagnosticmetadata: NSPM
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7BIT
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2015 20:52:10.5728
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR02MB1144
X-Microsoft-Exchange-Diagnostics: 1;DB5PR02MB0840;2:XnVUlBhRXAjNbISYcBALKAFsfXtbt1Ny2VHfgqDADxPoTzDTHcahMOB16+R5yhk6J53G/b8TrCPg/VkN9+Ojw/cDaREu4+u0nZDnq6Q02CFFYxUQV4UVms1PEyQxTbj18EdxysbgDRBPWuz0ePJbDFmclsJ3b9ijuN/I3Cos4jY=;23:PD571p75y+ZNIFh0/uZKQHJMHmw/hR3qBFN521k8ReyCKu0YR+vaQHtaWqWW0yzAI3dcslq+5o2AP6Hdp/8gGewdQc1WjiqHCkat40TaqSnZfzFRFzRCwYURzV541xkNhNDwExau4+x6C/6rAM5O0DRiWEznSzWTUsGhldgKhOPPdFJeQzkOrSda5D00XwM2
X-OriginatorOrg: ezchip.com
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Content-Length: 1268
Lines: 36

>From: Thomas Gleixner <tglx@linutronix.de>
>Sent: Saturday, November 7, 2015 1:38 PM

>> +     /*
>> +      * GIM interrupt select type for
>> +      * dbg_lan TX and RX interrupts
>> +      * should be type 1
>> +      * type 0 = IRQ line 6
>> +      * type 1 = IRQ line 7
>> +      */
>> +     gim_p_int_dst.is = 1;

>More magic structs to set a single bit, right?
I will replace all such magic with macros.

>> +     ienb &= ~(1 << data->irq);

>You should not rely on data->irq ever. It's the Linux interrupt number
>and it does not necessarily have a 1:1 mapping to the hardware
>nterrupt number. Its working for legacy domains, but there
>data->hwirq is set up for you as well.
Thanks, I will use data->hwirq instead of data->irq.


>> +     write_aux_reg(AUX_IENABLE, ienb);

>I can see how that works for per cpu interrupts, but what happens if
>two cpus run that concurrent for two different interrupts?

Each CPU got its own HW copy of auxiliary register IENABLE, so concurrent access won't be a trouble.
 
-Noam--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/