Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758269AbbKGXx3 (ORCPT ); Sat, 7 Nov 2015 18:53:29 -0500 Received: from www.linutronix.de ([62.245.132.108]:36044 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758248AbbKGXxV (ORCPT ); Sat, 7 Nov 2015 18:53:21 -0500 Date: Sun, 8 Nov 2015 00:52:33 +0100 (CET) From: Thomas Gleixner To: Noam Camus cc: "linux-snps-arc@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Tal Zilcer , Gil Fruchter , Chris Metcalf , Jason Cooper , Marc Zyngier Subject: Re: [PATCH v2 04/19] irqchip: add nps Internal and external irqchips In-Reply-To: Message-ID: References: <1446297327-16298-1-git-send-email-noamc@ezchip.com> <1446893557-29748-5-git-send-email-noamc@ezchip.com>, User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 693 Lines: 22 Noam, On Sat, 7 Nov 2015, Noam Camus wrote: > >From: Thomas Gleixner > >> + write_aux_reg(AUX_IENABLE, ienb); > > >I can see how that works for per cpu interrupts, but what happens if > >two cpus run that concurrent for two different interrupts? > > Each CPU got its own HW copy of auxiliary register IENABLE, so > concurrent access won't be a trouble. Please put a comment into the code explaining it. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/