Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751662AbbKIWCh (ORCPT ); Mon, 9 Nov 2015 17:02:37 -0500 Received: from casper.infradead.org ([85.118.1.10]:59140 "EHLO casper.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751201AbbKIWCg (ORCPT ); Mon, 9 Nov 2015 17:02:36 -0500 Date: Mon, 9 Nov 2015 23:02:32 +0100 From: Peter Zijlstra To: gratian.crisan@ni.com Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, Ingo Molnar , "H . Peter Anvin" , x86@kernel.org, Borislav Petkov , Josh Cartwright , gratian@gmail.com Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error Message-ID: <20151109220232.GO17308@twins.programming.kicks-ass.net> References: <1447099142-10220-1-git-send-email-gratian.crisan@ni.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1447099142-10220-1-git-send-email-gratian.crisan@ni.com> User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 773 Lines: 21 On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.crisan@ni.com wrote: > The Intel Xeon E5 processor family suffers from errata[1] BT81: > +#ifdef CONFIG_X86_TSC > + /* > + * Xeon E5 BT81 errata: TSC is not affected by warm reset. > + * The TSC registers for CPUs other than CPU0 are not cleared by a warm > + * reset resulting in a constant offset error. > + */ > + if ((c->x86 == 6) && (c->x86_model == 0x3f)) > + set_cpu_bug(c, X86_BUG_TSC_OFFSET); > +#endif That's hardly a family, that's just one, Haswell server. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/