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Date: Tue, 10 Nov 2015 14:41:59 -0600
Message-ID: <CAKA=qzZNQqzL2sN5WFHog42ak3tsBmj6-Jy=nBoLC8EXn+aOdw@mail.gmail.com>
Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs
 with offset error
From: Josh Hunt <joshhunt00@gmail.com>
To: Gratian Crisan <gratian.crisan@ni.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@redhat.com>,
        "H . Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        Borislav Petkov <bp@alien8.de>, Josh Cartwright <joshc@ni.com>,
        gratian@gmail.com
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On Tue, Nov 10, 2015 at 1:47 PM, Gratian Crisan <gratian.crisan@ni.com> wrote:
>
> The observed behavior does seem to match BT81 errata i.e. the TSC does
> not get reset on warm reboots and it is otherwise stable.
>
If you have a simple testcase to reproduce the problem I'd be
interested in seeing it.

-- 
Josh
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