Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752234AbbKJWGv (ORCPT ); Tue, 10 Nov 2015 17:06:51 -0500 Received: from mout.kundenserver.de ([212.227.17.13]:52930 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752070AbbKJWGs (ORCPT ); Tue, 10 Nov 2015 17:06:48 -0500 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Sinan Kaya , Abhijit Mahajan , linux-scsi@vger.kernel.org, Nagalakshmi Nandigama , jcm@redhat.com, timur@codeaurora.org, "James E.J. Bottomley" , linux-kernel@vger.kernel.org, Sreekanth Reddy , Praveen Krishnamoorthy , Hannes Reinecke , linux-arm-msm@vger.kernel.org, agross@codeaurora.org, MPT-FusionLinux.pdl@avagotech.com, cov@codeaurora.org Subject: Re: [PATCH V2 1/3] scsi: mptxsas: try 64 bit DMA when 32 bit DMA fails Date: Tue, 10 Nov 2015 23:06:03 +0100 Message-ID: <3710077.X1fITqqHih@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <56425A6B.2070900@codeaurora.org> References: <1447034266-28003-1-git-send-email-okaya@codeaurora.org> <3742888.Lmg2Y11mdz@wuerfel> <56425A6B.2070900@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:GhQmNfzkA38Aqp0gb1eK1v8t+eEIFlCzEElFEvNKb3nUI6sJUGE p1kgUpZOI1GuiWvcFv2zZ6zfL48Q8trOcvZo5hJRP9ytyPEqRTL/xPnrk6HcqScKqbfgbRX LKHD2CQAiDdsjzSjf+WjvJDlq12g56/+RE0FZDQnLvRRlUn6gGPsKoWkI1DGneoSVxwF2zC Igs5H5au1wlZc/Dk9nTdg== X-UI-Out-Filterresults: notjunk:1;V01:K0:eSppb46drbk=:XKLTAjnoZ3RrhHFa3psMhk P688jNN22Twx37myr17G58sNIDL5cf3Nv0dl6oRy+mygV4FdAhOAwMmPBDJgqW2Pu8COrf6Rv eRw4nCJwVEXce964dpd6CGD9eBh6vwYX3KsY63iVSP+SBdBUjPIBfyP6yvUPEuiSTHuWGjtNg cPSPwq9P5XP8yez8IyQOcJ2E7iMyB1gQuRsURT3fbIMBdfL4HzB8zw+scVat+dN1+bNESvywj d/zkKp/93j7kgJED33PSV0d1aiL9ZcOy0ky2Q/Ta4ZMe0PFJNomEUZPLuaGDTBuwRlv7Djny7 lx5pmd6uXG6ak1jIe5FDFpZS+5dnZMV384xjomVQ6MuS6IVprTeQyU4TSSjSu4P1CeS/x3F26 iUHePdAEqmZD1TAU7bkaNXOtzl8xmBxpdUKf6aaXzCARG9y4Kkg7/kAAuzR8G+CYCyjF6TT9Z IRbMJo8K7mN4/WTWpYhHCinUo1LXZ6EKEK4Ssg/Clwnq3DbxqJjyLZdmBrbCWJMFGbXW7h0D4 KIqZ6oxlLNMZCQt61p1vp3hIUgKqZebqeO4wEjBZqw7dU4Qn3pFDR0hy0mgDtQrCOfcrJaeSY EirNsC7z9g+K9Ks96mpUUUuznL42w02PmQeamGJAqgLPGLGz8iuyUQdbiselGw3TM8qczttIy a9aeAd3Z/cpEoD5r36mDsEd5SPQgmJ7FpVQrX7gLOldrCo2a3Y5tgsre0ET2RFLB3wCLqYf5r kxM8f+Lk0A/FoaSk Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2835 Lines: 60 On Tuesday 10 November 2015 15:58:19 Sinan Kaya wrote: > > On 11/10/2015 2:56 PM, Arnd Bergmann wrote: > >> The ACPI IORT table declares whether you enable IOMMU for a particular > >> >device or not. The placement of IOMMU HW is system specific. The IORT > >> >table gives the IOMMU HW topology to the operating system. > > This sounds odd. Clearly you need to specify the IOMMU settings for each > > possible PCI device independent of whether the OS actually uses the IOMMU > > or not. > > There are provisions to have DMA mask in the PCIe host bridge not at the > PCIe device level inside IORT table. This setting is specific for each > PCIe bus. It is not per PCIe device. Same thing, I meant the bootloader must provide all the information that is needed to use the IOMMU on all PCI devices. I don't care where the IOMMU driver gets that information. Some IOMMUs require programming a bus/device/function specific number into the I/O page tables, and they might not always have the same algorithm to map from the PCI numbers into their own number space. > It is assumed that the endpoint device driver knows the hardware for > PCIe devices. The driver can also query the supported DMA bits by this > platform via DMA APIs and will request the correct DMA mask from the DMA > subsystem (surprise!). I know how the negotiation works. Note that dma_get_required_mask() will only tell you what mask the device needs to access all of memory, while both the device and bus may have additional limitations, and there is not always a solution. > >In a lot of cases, we want to turn it off to get better performance > > when the driver has set a DMA mask that covers all of RAM, but you > > also want to enable the IOMMU for debugging purposes or for device > > assignment if you run virtual machines. The bootloader doesn't know how > > the device is going to be used, so it cannot define the policy here. > > I think we'll end up adding a virtualization option to the UEFI BIOS > similar to how Intel platforms work. Based on this switch, we'll end up > patching the ACPI table. > > If I remove the IORT entry, then the device is in coherent mode with > device accessing the full RAM range. > > If I have the IORT table, the device is in IOMMU translation mode. > > Details are in the IORT spec. I think that would suck a lot more than being slightly out of spec regarding SBSA if you make the low PCI addresses map to the start of RAM. Asking users to select a 'virtualization' option based on what kind of PCI device and kernel version they have is a major hassle. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/