Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933346AbbKMKRQ (ORCPT ); Fri, 13 Nov 2015 05:17:16 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:15842 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932189AbbKMKQr (ORCPT ); Fri, 13 Nov 2015 05:16:47 -0500 X-AuditID: cbfec7f4-f79c56d0000012ee-1b-5645b88cb84e Subject: Re: [PATCH v5 5/9] ARM: EXYNOS: split up exynos4 SoC specific PMU data To: Pankaj Dubey , linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org References: <1447406983-27835-1-git-send-email-pankaj.dubey@samsung.com> <1447406983-27835-6-git-send-email-pankaj.dubey@samsung.com> Cc: kgene.kim@samsung.com, thomas.ab@samsung.com, amitdanielk@gmail.com, olof@lixom.net, khilman@linaro.org, arnd@arndb.de From: Krzysztof Kozlowski Message-id: <5645B88C.1020104@samsung.com> Date: Fri, 13 Nov 2015 19:16:44 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-version: 1.0 In-reply-to: <1447406983-27835-6-git-send-email-pankaj.dubey@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsVy+t/xq7o9O1zDDGZNlrb4uPolm8XfScfY LV6/MLToXXCVzeLr4RWMFpseX2O1uLxrDpvF594jjBYzzu9jsjh1/TObxaKtX9gtOpYxOvB4 /P41idFj56y77B53ru1h89i8pN7jyokmVo++LasYPT5vkgtgj+KySUnNySxLLdK3S+DK+Ny9 grngcmbF+uuaDYxng7sYOTkkBEwk7q9czA5hi0lcuLeeDcQWEljKKDHneVQXIxeQ/YVRYlPz AyaQhLCAv8TlWZPBbBGBDYwSV05lQRS1M0r8PPUdLMEsUCNx+tMVRhCbTcBYYvPyJWBTeQW0 JBoutbKA2CwCqhI7lswAi4sKREhMnNDAClEjKPFj8j2wGk4BT4mTl64CxTmAZupJ3L+oBTFe XmLzmrfMExgFZiHpmIVQNQtJ1QJG5lWMoqmlyQXFSem5hnrFibnFpXnpesn5uZsYIRHyZQfj 4mNWhxgFOBiVeHiTnrmECbEmlhVX5h5ilOBgVhLhXQwS4k1JrKxKLcqPLyrNSS0+xCjNwaIk zjt31/sQIYH0xJLU7NTUgtQimCwTB6dUA2P2unPqzEIK2VM7HSZMMxX9lRB+rvn0/92n2lVr J2bop4bfj5ggIVRwsPb5zTVSP0/3luf8KalIem21ou7sBeWOi1xbVovv+90Wrb79favr81Uv t/Fv4FqRtuCKXhi/uNGGfbYxXiZbFaZyP/Xeq/n21pQvdzuD9G5qBW+/aSh0v0zPTNMjer8S S3FGoqEWc1FxIgBbg2uBjAIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 13488 Lines: 285 On 13.11.2015 18:29, Pankaj Dubey wrote: > This patch splits up mach-exynos/pmu.c file, and moves exynos4210, > exynos4412 and exynos4212 PMU configuration data and functions handing > data into a common exynos4 SoC specific PMU file mach-exynos/exynos4-pmu.c. > > Signed-off-by: Pankaj Dubey > Reviewed-by: Krzysztof Kozlowski > --- > arch/arm/mach-exynos/Makefile | 2 +- > arch/arm/mach-exynos/exynos-pmu.h | 3 + > arch/arm/mach-exynos/exynos4-pmu.c | 223 +++++++++++++++++++++++++++++++++++++ > arch/arm/mach-exynos/pmu.c | 207 ---------------------------------- > 4 files changed, 227 insertions(+), 208 deletions(-) > create mode 100644 arch/arm/mach-exynos/exynos4-pmu.c > > diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile > index e869f86..8969683 100644 > --- a/arch/arm/mach-exynos/Makefile > +++ b/arch/arm/mach-exynos/Makefile > @@ -9,7 +9,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree) > > # Core > > -obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o exynos3250-pmu.o > +obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o exynos3250-pmu.o exynos4-pmu.o > > obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o > obj-$(CONFIG_PM_SLEEP) += suspend.o > diff --git a/arch/arm/mach-exynos/exynos-pmu.h b/arch/arm/mach-exynos/exynos-pmu.h > index 5d09fa3..3d21aad 100644 > --- a/arch/arm/mach-exynos/exynos-pmu.h > +++ b/arch/arm/mach-exynos/exynos-pmu.h > @@ -33,6 +33,9 @@ struct exynos_pmu_data { > extern void __iomem *pmu_base_addr; > /* list of all exported SoC specific data */ > extern const struct exynos_pmu_data exynos3250_pmu_data; > +extern const struct exynos_pmu_data exynos4210_pmu_data; > +extern const struct exynos_pmu_data exynos4212_pmu_data; > +extern const struct exynos_pmu_data exynos4412_pmu_data; > > extern void pmu_raw_writel(u32 val, u32 offset); > extern u32 pmu_raw_readl(u32 offset); > diff --git a/arch/arm/mach-exynos/exynos4-pmu.c b/arch/arm/mach-exynos/exynos4-pmu.c > new file mode 100644 > index 0000000..4b0a79e > --- /dev/null > +++ b/arch/arm/mach-exynos/exynos4-pmu.c > @@ -0,0 +1,223 @@ > +/* > + * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS4 - CPU PMU(Power Management Unit) support > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > + > +#include "exynos-pmu.h" > + > +static const struct exynos_pmu_conf exynos4210_pmu_config[] = { > + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ > + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, > + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, > + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } }, > + { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } }, > + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, > + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, > + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, > + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { PMU_TABLE_END,}, > +}; > + > +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { > + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, > + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, > + { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } }, > + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } }, > + /* XXX_OPTION register should be set other field */ > + { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } }, > + { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } }, > + { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } }, > + { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } }, > + { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, > + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, > + { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, > + { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } }, > + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } }, > + { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, > + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, > + { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } }, > + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, > + { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } }, > + { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } }, > + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, > + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, > + { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, > + { PMU_TABLE_END,}, > +}; > + > +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { > + { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, > + { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, > + { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, > + { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, > + { PMU_TABLE_END,}, > +}; > + > +const struct exynos_pmu_data exynos4210_pmu_data = { > + .pmu_config = exynos4210_pmu_config, > +}; > + > +const struct exynos_pmu_data exynos4212_pmu_data = { > + .pmu_config = exynos4x12_pmu_config, > +}; > + > +const struct exynos_pmu_data exynos4412_pmu_data = { > + .pmu_config = exynos4x12_pmu_config, > + .pmu_config_extra = exynos4412_pmu_config, > +}; > + Unnecessary new line at EOF. No need to fix (I can fix it while applying), unless you will re-spin the patchset (for v6). Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/