Date: Fri, 13 Nov 2015 21:43:38 +0100
From: Peter Zijlstra <peterz@infradead.org>
To: Gratian Crisan <gratian.crisan@ni.com>
Cc: Josh Hunt <joshhunt00@gmail.com>, Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@redhat.com>,
        "H . Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        Borislav Petkov <bp@alien8.de>, Josh Cartwright <joshc@ni.com>,
        gratian@gmail.com
Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs
 with offset error
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On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote:
> I also wrote a small C utility[1], with a bit of code borrowed from the
> kernel, for reading the TSC on all CPUs. It starts a high priority
> thread per CPU, tries to synchronize them and prints out the TSC values
> and their offset with regards to CPU0.
> It can be called from a SysV init shell script[2] at the beginning of
> the boot process and right before a reboot to save the values in a file.

Could you also read and print TSC_ADJUST (msr 0x3b) ? This would tell us
if for example your BIOS messed it up.

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