Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs
 with offset error
To: Peter Zijlstra <peterz@infradead.org>, gratian.crisan@ni.com
References: <1447099142-10220-1-git-send-email-gratian.crisan@ni.com>
 <20151109220232.GO17308@twins.programming.kicks-ass.net>
Cc: Thomas Gleixner <tglx@linutronix.de>, linux-kernel@vger.kernel.org,
        Ingo Molnar <mingo@redhat.com>, "H . Peter Anvin" <hpa@zytor.com>,
        x86@kernel.org, Borislav Petkov <bp@alien8.de>,
        Josh Cartwright <joshc@ni.com>, gratian@gmail.com
From: Dave Hansen <dave.hansen@intel.com>
Message-ID: <56465279.2010502@intel.com>
Date: Fri, 13 Nov 2015 13:13:29 -0800
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On 11/09/2015 02:02 PM, Peter Zijlstra wrote:
> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.crisan@ni.com wrote:
>> The Intel Xeon E5 processor family suffers from errata[1] BT81:
> 
>> +#ifdef CONFIG_X86_TSC
>> +	/*
>> +	 * Xeon E5 BT81 errata: TSC is not affected by warm reset.
>> +	 * The TSC registers for CPUs other than CPU0 are not cleared by a warm
>> +	 * reset resulting in a constant offset error.
>> +	 */
>> +	if ((c->x86 == 6) && (c->x86_model == 0x3f))
>> +		set_cpu_bug(c, X86_BUG_TSC_OFFSET);
>> +#endif
> 
> That's hardly a family, that's just one, Haswell server.

How did you come up with that x86_model?  The document you linked to
claimes that "Extended Model" is 0010b and "Model Number" is 1101b, so
the x86_model you are looking for should be 0x2d.

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