Message-ID: <564DA7C2.8060002@huawei.com>
Date: Thu, 19 Nov 2015 18:43:14 +0800
From: "Wangnan (F)" <wangnan0@huawei.com>
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To: Ingo Molnar <mingo@kernel.org>
CC: Jiri Olsa <jolsa@kernel.org>, Arnaldo Carvalho de Melo <acme@kernel.org>,
        David Ahern <dsahern@gmail.com>, Peter Zijlstra <peterz@infradead.org>,
        Milian Wolff <milian.wolff@kdab.com>, <linux-kernel@vger.kernel.org>,
        pi3orama <pi3orama@163.com>, lizefan 00213767 <lizefan@huawei.com>
Subject: Re: [BUG REPORT] perf tools: x86_64: Broken calllchain when sampling
 taken at 'callq' instruction
References: <564C26C4.2040603@huawei.com> <564C3011.8090002@huawei.com> <20151118082033.GA24726@gmail.com> <564C3A0E.3030502@huawei.com> <564C3BAA.4040806@huawei.com> <20151119063709.GA14852@gmail.com> <564D6FF9.3030105@huawei.com> <20151119102300.GA2830@gmail.com>
In-Reply-To: <20151119102300.GA2830@gmail.com>
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On 2015/11/19 18:23, Ingo Molnar wrote:
> * Wangnan (F) <wangnan0@huawei.com> wrote:
>
>>
>> On 2015/11/19 14:37, Ingo Molnar wrote:
>>> * Wangnan (F) <wangnan0@huawei.com> wrote:
>>>
>>>>> perf cmdline is
>>>>>
>>>>> # ./pref record  -g -F 9 --call-graph dwarf ./test_dwarf_unwind
>>>>>
>>>>> Use default events, precise_ip == 2 so uses PEBS.
>>>>>
>>>> Testetd 'cycles', 'cycles:p' and 'cycles:pp'. Only 'cycles:pp' captures
>>>> sample at callq. So maybe a PEBS problem?
>>> Well, that's how our PEBS sampling works: we roll back the instruction pointer to
>>> point at the instruction generating the sample. The state itself is
>>> post-instruction.
>> Just for curiosity:
>>
>> how the interrupted process continue to execute, when the PC
>> saved in pt_regs still pointed to 'callq' but SP and stack has
>> already changes? Do we fix it in kernel, or by hardware?
> PEBS is an asynchronous hardware tracing mechanism, when batched PEBS is used it
> might not even result in any interruption of execution. The 'pt_regs' does not
> necessarily correspond to an interrupted, restartable context - we take the RIP
> from the PEBS machinery and also use LBR and disassembly to determine the previous
> instruction, before reporting it to user-space.

You mean __intel_pmu_pebs_event(), which generates many perf_events?
Then their output are based on a same user stack, and could be error,
because the instruction has finished, and user stack could be modified.
Right?

Also, why not fixing rsp in kernel if that instruction is a 'callq'?
For avoiding instruction decoding?

Thank you.

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