References: <1447099142-10220-1-git-send-email-gratian.crisan@ni.com> <20151109220232.GO17308@twins.programming.kicks-ass.net> <CAKA=qzarnUUmZb7DQE+u0Dei3F+FQNoL2bak_-dV9D9+3L=itQ@mail.gmail.com> <CAKA=qzbqN--3Ra+syiwM17z_Nue9aH9Ec1-pz-QwWt7OCHcbrA@mail.gmail.com> <87mvultz5f.fsf@spline.amer.corp.natinst.com> <CAKA=qzZNQqzL2sN5WFHog42ak3tsBmj6-Jy=nBoLC8EXn+aOdw@mail.gmail.com> <87io58tufu.fsf@spline.amer.corp.natinst.com> <20151113204338.GA9928@worktop.ger.corp.intel.com>
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From: Gratian Crisan <gratian.crisan@ni.com>
To: Peter Zijlstra <peterz@infradead.org>
CC: Gratian Crisan <gratian.crisan@ni.com>, Josh Hunt <joshhunt00@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@redhat.com>,
        "H . Peter Anvin" <hpa@zytor.com>, <x86@kernel.org>,
        Borislav Petkov <bp@alien8.de>, Josh Cartwright <joshc@ni.com>,
        <gratian@gmail.com>
Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error
In-Reply-To: <20151113204338.GA9928@worktop.ger.corp.intel.com>
Date: Thu, 19 Nov 2015 13:04:30 -0600
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Peter Zijlstra writes:

> On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote:
>> I also wrote a small C utility[1], with a bit of code borrowed from the
>> kernel, for reading the TSC on all CPUs. It starts a high priority
>> thread per CPU, tries to synchronize them and prints out the TSC values
>> and their offset with regards to CPU0.
>> It can be called from a SysV init shell script[2] at the beginning of
>> the boot process and right before a reboot to save the values in a file.
>
> Could you also read and print TSC_ADJUST (msr 0x3b) ? This would tell us
> if for example your BIOS messed it up.

We've gathered some more information on this:

1. We were able to confirm that the TSC_ADJUST is set for CPU0 before
the bootloader or kernel start. Using an EFI shell to read MSR 0x3b
shows:
 0: 0xFFFFFFFFAD999CCB
 1: 0x0000000000000000
 2: 0x0000000000000000
 3: 0x0000000000000000
 4: 0x0000000000000000
 5: 0x0000000000000000
 6: 0x0000000000000000
 7: 0x0000000000000000

2. We were also able to reproduce this behavior on a Dell Precision
T5810 workstation PC. Relevant /proc/cpuinfo below[1]. Additionally we
have observed the same behavior on an off the shelf motherboard
equipped with a Haswell-E similar to the Haswell-EP we originally saw
this on.

We are still trying to figure out what in the boot chain sets the CPU0's
TSC_ADJUST i.e. BIOS, something pre-BIOS and how to proceed from there.

Thanks,
        Gratian

[1]
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 63
model name      : Intel(R) Core(TM) i7-5930K CPU @ 3.50GHz
stepping        : 2
microcode       : 0x27
cpu MHz         : 1200.117
cache size      : 15360 KB
physical id     : 0
siblings        : 12
core id         : 0
cpu cores       : 6
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 15
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid
bogomips        : 6983.91
clflush size    : 64
cache_alignment : 64
address sizes   : 46 bits physical, 48 bits virtual
power management:
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