Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161577AbbKSUoc (ORCPT ); Thu, 19 Nov 2015 15:44:32 -0500 Received: from mail-ob0-f180.google.com ([209.85.214.180]:34320 "EHLO mail-ob0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934536AbbKSUo2 (ORCPT ); Thu, 19 Nov 2015 15:44:28 -0500 MIME-Version: 1.0 In-Reply-To: <1577961.dn1fd8r35p@avalon> References: <1447958344-836-1-git-send-email-geert+renesas@glider.be> <1447958344-836-3-git-send-email-geert+renesas@glider.be> <1577961.dn1fd8r35p@avalon> Date: Thu, 19 Nov 2015 21:44:27 +0100 X-Google-Sender-Auth: ge9RWiVdk7KO_amAuuYW1dTY7QU Message-ID: Subject: Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support From: Geert Uytterhoeven To: Laurent Pinchart Cc: Geert Uytterhoeven , Greg Kroah-Hartman , Simon Horman , Magnus Damm , Yoshinori Sato , "linux-serial@vger.kernel.org" , Linux-sh list , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1812 Lines: 42 Hi Laurent, On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote: > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: >> Amend the DT bindings to include the optional clock sources for the Baud >> Rate Generator for External Clock (BRG), as found on some SCIF variants >> and on HSCIF. >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> @@ -46,6 +46,12 @@ Required properties: >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> - "hsck" for the optional external clock input (on HSCIF), >> - "sck" for the optional external clock input (on other variants). >> + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) >> + (some SCIF and HSCIF), additional clocks may be specified: >> + - "int_clk" for the optional internal clock source for the frequency >> + divider (typically the (AXI or SHwy) bus clock), > > Isn't this always the same clock as the SCIF functional clock ? (On R-Car Gen2/3) No, SCIF uses different parents for fck (p) and int_clk (zs). HSCIF uses the same parents though (zs). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/