Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934990AbbKTH63 (ORCPT ); Fri, 20 Nov 2015 02:58:29 -0500 Received: from mail-oi0-f43.google.com ([209.85.218.43]:33284 "EHLO mail-oi0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754664AbbKTH61 (ORCPT ); Fri, 20 Nov 2015 02:58:27 -0500 MIME-Version: 1.0 In-Reply-To: <3455553.NW0SflpMPP@avalon> References: <1447958344-836-1-git-send-email-geert+renesas@glider.be> <1577961.dn1fd8r35p@avalon> <3455553.NW0SflpMPP@avalon> Date: Fri, 20 Nov 2015 08:58:25 +0100 X-Google-Sender-Auth: _hnoCmDoaAQNHl0p4tCUBNGYZXw Message-ID: Subject: Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support From: Geert Uytterhoeven To: Laurent Pinchart Cc: Geert Uytterhoeven , Greg Kroah-Hartman , Simon Horman , Magnus Damm , Yoshinori Sato , "linux-serial@vger.kernel.org" , Linux-sh list , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2444 Lines: 59 Hi Laurent, On Thu, Nov 19, 2015 at 10:13 PM, Laurent Pinchart wrote: > On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote: >> On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote: >> > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: >> >> Amend the DT bindings to include the optional clock sources for the Baud >> >> Rate Generator for External Clock (BRG), as found on some SCIF variants >> >> and on HSCIF. >> >> >> >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> >> >> >> @@ -46,6 +46,12 @@ Required properties: >> >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> >> - "hsck" for the optional external clock input (on HSCIF), >> >> - "sck" for the optional external clock input (on other variants). >> >> >> >> + On UARTs equipped with a Baud Rate Generator for External Clock >> >> (BRG) >> >> + (some SCIF and HSCIF), additional clocks may be specified: >> >> + - "int_clk" for the optional internal clock source for the >> >> frequency >> >> + divider (typically the (AXI or SHwy) bus clock), >> > >> > Isn't this always the same clock as the SCIF functional clock ? >> >> (On R-Car Gen2/3) >> >> No, SCIF uses different parents for fck (p) and int_clk (zs). > > Right, my bad. > > Should we rename "int_clk" to something that makes it explicit that the clock > is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We > probably don't need to keep the _clk suffix as it's quite evident that a clock > name refers to a clock. The documentation always uses the SoC-specific explicit clock name (e.g. zs s3d1, or clks), or just "internal clock", so I used "int_clk". But I agree "int_brg" sounds better. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/