Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1163208AbbKTRWa (ORCPT ); Fri, 20 Nov 2015 12:22:30 -0500 Received: from mail-lb0-f171.google.com ([209.85.217.171]:32792 "EHLO mail-lb0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760457AbbKTRW3 (ORCPT ); Fri, 20 Nov 2015 12:22:29 -0500 From: Jacob Siverskog To: Michael Turquette , Stephen Boyd , Sebastian Hesselbarth , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Belisko Marek , Jacob Siverskog Subject: [PATCH v2] clk: si5351: Add PLL soft reset Date: Fri, 20 Nov 2015 18:22:16 +0100 Message-Id: <1448040137-21400-1-git-send-email-jacob@teenage.engineering> X-Mailer: git-send-email 2.6.3 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 892 Lines: 28 Hi! A representative from SiLabs writes: "All the currently published versions of the Si5351 (v1.0) and AN619 (v0.6) do not include the “Si5351A/C only” disclaimer. Based on this and our current understanding, I see no issue performing a PLLB reset for ‘B’ type devices.". Hence, it should not be any issues always performing the PLL reset. Changes in v2: - Output disabling and power down removed in order to prevent breaking systems requiring always-enabled clocks - Cosmetic changes Jacob Jacob Siverskog (1): clk: si5351: Add PLL soft reset drivers/clk/clk-si5351.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.6.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/