Subject: Re: [PATCH 02/14] irqchip: irq-pic32-evic: Add support for PIC32
 interrupt controller
To: Marc Zyngier <marc.zyngier@arm.com>
References: <1448065205-15762-1-git-send-email-joshua.henderson@microchip.com>
 <1448065205-15762-3-git-send-email-joshua.henderson@microchip.com>
 <20151122114530.10bca210@arm.com>
CC: <linux-kernel@vger.kernel.org>, <linux-mips@linux-mips.org>,
        Cristian Birsan <cristian.birsan@microchip.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>
From: Joshua Henderson <joshua.henderson@microchip.com>
Message-ID: <5655FC74.9090204@microchip.com>
Date: Wed, 25 Nov 2015 11:22:44 -0700
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On 11/22/2015 4:45 AM, Marc Zyngier wrote:
> On Fri, 20 Nov 2015 17:17:14 -0700
> Joshua Henderson <joshua.henderson@microchip.com> wrote:
> 
> Joshua, Cristian,
> 
>> From: Cristian Birsan <cristian.birsan@microchip.com>
>>
>> This adds support for the EVIC present on a PIC32MZDA.
>>
>> The following features are supported:
>>  - DT properties for EVIC and for devices that use interrupt lines
>>  - persistent and non-persistent interrupt handling
>>  - Priority, sub-priority and polariy settings for each interrupt line
>>  - irqdomain support
>>
> 
> I haven't reviewed the code yet, but the fact that you allow (and
> actually request) the interrupt priorities to be encoded in the DT
> raises some concerns:
> 
> - Aren't priorities entirely under software control (and hence don't
>   belong in DT)?

These are hardware priorities configured by software.  They arbitrate pending hardware interrupts to the CPU.  We can agree that DT is probably not the best place for this configuration.  They will be removed from the binding.

> - More crucially, how do you deal with nested interrupts when you have
>   interrupts running at different priorities? Most parts of Linux
>   cannot cope with that without additional support.
> 

We do not support nested interrupts.

> Thanks,
> 
> 	M.
> 


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