Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752181AbbKZKuj (ORCPT ); Thu, 26 Nov 2015 05:50:39 -0500 Received: from unicorn.mansr.com ([81.2.72.234]:45151 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751014AbbKZKuh convert rfc822-to-8bit (ORCPT ); Thu, 26 Nov 2015 05:50:37 -0500 From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= To: Mason Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: Re: [PATCH 2/2] irqchip: add support for Sigma Designs SMP86xx interrupt controller References: <1447958026-3015-1-git-send-email-mans@mansr.com> <1447958026-3015-3-git-send-email-mans@mansr.com> <56558E13.6030703@free.fr> <5655A537.3040707@free.fr> <5656DE33.4040400@free.fr> Date: Thu, 26 Nov 2015 10:50:29 +0000 In-Reply-To: <5656DE33.4040400@free.fr> (Mason's message of "Thu, 26 Nov 2015 11:25:55 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1637 Lines: 50 Mason writes: > On 25/11/2015 13:12, M?ns Rullg?rd wrote: > >> Mason writes: >> >>>> + status_lo = intc_readl(chip, chip->ctl + IRQ_STATUS); >>>> + status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS); >>> >>> In my local branch, I wrote: >>> >>> #define IRQ_CTL_LO 0 >>> >>> status_lo = intc_readl(chip, chip->ctl + IRQ_CTL_LO + IRQ_STATUS); >>> status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS); >>> >>> (I'm a sucker for symmetry) >> >> Nothing wrong with a little symmetry, though in this case I think the >> extra macro only confuses matters. > > It's your call :-) > > In my mind, the fact that the status_lo register sits at offset 0 is > just an accident. It's just that something has to sit at offset 0. > (Maybe I should tell the HW guys to put nothing at offset 0, and start > the actual register block at offset 4. /That/ would be unexpected.) > > Another way to look at it is: > > There are two 4-register blocks (LO and HI) each containing registers > {status,rawstat,enableset,enableclr}. > > Block LO starts at offset 0x0 > Block HI starts at offset 0x18 > > and then there are the intra offsets for the 4 registers in the block. When I wrote it, I was thinking of IRQ_CTL_HI as the offset to add to a low register to get the corresponding high one. I think that's what you said there. -- M?ns Rullg?rd mans@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/