From: Duan Andy <fugang.duan@freescale.com>
To: =?utf-8?B?TG90aGFyIFdhw59tYW5u?= <LW@KARO-electronics.de>
CC: Andrew Lunn <andrew@lunn.ch>, "David S. Miller" <davem@davemloft.net>,
        Fabio Estevam <Fabio.Estevam@freescale.com>,
        Kevin Hao <haokexin@gmail.com>, Lucas Stach <l.stach@pengutronix.de>,
        Philippe Reynes <tremyfr@gmail.com>,
        Russell King <rmk+kernel@arm.linux.org.uk>,
        Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        Stefan Agner <stefan@agner.ch>
Subject: RE: [PATCH] net: fec: fix enet_out clock handling
Thread-Topic: [PATCH] net: fec: fix enet_out clock handling
Thread-Index: AQHRKRk2yV8ik/j4gEuk1Xs5hLkIYJ6xaVuggAK83oCAAAYTEA==
Date: Mon, 30 Nov 2015 07:31:19 +0000
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From: Lothar Waßmann <LW@KARO-electronics.de> Sent: Monday, November 30, 2015 2:56 PM
> To: Duan Fugang-B38611
> Cc: Andrew Lunn; David S. Miller; Estevam Fabio-R49496; Kevin Hao; Lucas
> Stach; Philippe Reynes; Russell King; Uwe Kleine-K?nig; linux-
> kernel@vger.kernel.org; netdev@vger.kernel.org; Stefan Agner
> Subject: Re: [PATCH] net: fec: fix enet_out clock handling
> 
> Hi,
> 
> > From: Lothar Waßmann <LW@KARO-electronics.de> Sent: Friday, November
> > 27, 2015 9:39 PM
> > > To: Andrew Lunn; David S. Miller; Estevam Fabio-R49496; Kevin Hao;
> > > Lothar Waßmann; Lucas Stach; Duan Fugang-B38611; Philippe Reynes;
> > > Russell King; Uwe Kleine-König; linux-kernel@vger.kernel.org;
> > > netdev@vger.kernel.org; Stefan Agner
> > > Subject: [PATCH] net: fec: fix enet_out clock handling
> > >
> > > When ENET_OUT is being used as reference clock for an external PHY,
> > > the clock must not be disabled while the PHY is active. Otherwise
> > > the PHY may lose its internal state and require a reset to become
> functional again.
> > >
> > > A symptom for this bug is a network interface that constantly
> > > toggles between UP and DOWN state:
> > > fec 800f0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control
> > > rx/tx fec 800f0000.ethernet eth0: Link is Down fec 800f0000.ethernet
> eth0:
> > > Link is Up - 100Mbps/Full - flow control rx/tx fec 800f0000.ethernet
> eth0:
> > > Link is Down [...]
> > >
> > > Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
> > > ---
> > >  drivers/net/ethernet/freescale/fec_main.c | 34
> > > +++++++++++++------------
> > > ------
> > >  1 file changed, 14 insertions(+), 20 deletions(-)
> > >
> >
> > When MAC is not ready with clocks disabled,  it is not necessary to
> supply clock for PHY. In fact, PHY also is not ready, why does it need
> clock ?
> > For your problem, you must add PHY reset in your dts file to resolve
> your problem.
> >
> The phy-reset-gpio property is set in the DTB. But fec_reset_phy() which
> asserts the RESET is only called from within the probe() function.
> It should probably be called from fec_restart() instead?
> 
After enet_out clock enable, you can call fec_reset_phy() do phy reset.  Don't put it in .fec_restart() function because
Cable hotplug test cause phy registers reset to HW default status.

Regards,
Andy
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