Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754631AbbK3UxS (ORCPT ); Mon, 30 Nov 2015 15:53:18 -0500 Received: from proxima.lp0.eu ([81.2.80.65]:33592 "EHLO proxima.lp0.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752523AbbK3UxQ (ORCPT ); Mon, 30 Nov 2015 15:53:16 -0500 To: Michael Turquette , Stephen Boyd , Kevin Cernekee , Florian Fainelli , "devicetree@vger.kernel.org" From: Simon Arlott Cc: Linux Kernel Mailing List , linux-clk@vger.kernel.org, linux-mips@linux-mips.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding Message-ID: <565CB727.7030209@simon.arlott.org.uk> Date: Mon, 30 Nov 2015 20:52:55 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2971 Lines: 87 Add device tree binding for the BCM63xx's gated clocks. The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register. Signed-off-by: Simon Arlott --- .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file mode 100644 index 0000000..3f4ead1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt @@ -0,0 +1,58 @@ +Broadcom BCM63xx clocks + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +The BCM63xx contains clocks gated with a register. Clocks are indexed +by bits in the register and are active high. Clock gate bits are +interleaved with other status bits and configurable clocks in the same +register. + +Required properties: +- compatible: Should be "brcm,bcm-gate-clk", "brcm,bcm63xx-gate-clk" +- #clock-cells: Should be <1>. +- regmap: The register map phandle +- offset: Offset in the register map for the reboot register (in bytes) +- clocks: The external oscillator clock phandle + +Example: + +periph_clk: periph_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&periph_cntl>; + offset = <0x4>; + + #clock-cells = <1>; + clock-indices = + <1>, <2>, <3>, <4>, <5>, + <6>, <7>, <8>, <9>, <10>, + <11>, <12>, <13>, <14>, <15>, + <16>, <17>, <18>, <19>, <20>, + <27>, <31>; + clock-output-names = + "vdsl_qproc", "vdsl_afe", "vdsl", "mips", "wlan_ocp", + "dect", "fap0", "fap1", "sar", "robosw", + "pcm", "usbd", "usbh", "ipsec", "spi", + "hsspi", "pcie", "phymips", "gmac", "nand", + "tbus", "robosw250"; +}; + +timer_clk: timer_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&timer_cntl>; + offset = <0x4>; + + #clock-cells = <1>; + clock-indices = <17>, <18>; + clock-output-names = "uto_extin", "usb_ref"; +}; + +ehci0: usb@10002500 { + compatible = "brcm,bcm63168-ehci", "brcm,bcm63xx-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + big-endian; + interrupt-parent = <&periph_intc>; + interrupts = <10>; + clocks = <&periph_clk 13>, <&timer_clk 18>; + phys = <&usbh>; +}; -- 2.1.4 -- Simon Arlott -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/