Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753590AbbLENRQ (ORCPT ); Sat, 5 Dec 2015 08:17:16 -0500 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:39414 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752389AbbLENRM (ORCPT ); Sat, 5 Dec 2015 08:17:12 -0500 From: Chen-Yu Tsai To: Maxime Ripard , Emilio Lopez , Michael Turquette , Stephen Boyd , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH resend 1/6] clk: sunxi: Add DRAM gates support for sun4i-a10 Date: Sat, 5 Dec 2015 21:16:42 +0800 Message-Id: <1449321407-4531-2-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1449321407-4531-1-git-send-email-wens@csie.org> References: <1449321407-4531-1-git-send-email-wens@csie.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2402 Lines: 55 The A10/A20 share the same set of DRAM clock gates, which controls direct memory access for some peripherals. On the A10, bit 15 controls the system's DRAM clock output (possibly to the DRAM chips), which we need to keep on. On the A20 this has been moved to the DRAM controller, becoming a no-op. However it is still listed in the user manual, so add it anyway. Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-simple-gates.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 153ac72869e8..ef0b452806b1 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -57,6 +57,7 @@ Required properties: "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 + "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c index c8acc0612c15..f4da52b5ca0e 100644 --- a/drivers/clk/sunxi/clk-simple-gates.c +++ b/drivers/clk/sunxi/clk-simple-gates.c @@ -160,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk", sun4i_a10_ahb_init); CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk", sun4i_a10_ahb_init); + +static const int sun4i_a10_dram_critical_clocks[] __initconst = { + 15, /* dram_output */ +}; + +static void __init sun4i_a10_dram_init(struct device_node *node) +{ + sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks, + ARRAY_SIZE(sun4i_a10_dram_critical_clocks)); +} +CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk", + sun4i_a10_dram_init); -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/