Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932651AbbLGObP (ORCPT ); Mon, 7 Dec 2015 09:31:15 -0500 Received: from mail.kernel.org ([198.145.29.136]:38218 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754693AbbLGObL (ORCPT ); Mon, 7 Dec 2015 09:31:11 -0500 Date: Mon, 7 Dec 2015 08:31:02 -0600 From: Rob Herring To: Jean-Francois Moine Cc: Maxime Ripard , Chen-Yu Tsai , Michael Turquette , Stephen Boyd , Linus Walleij , devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?iso-8859-1?Q?L=F3pez?= , Reinder de Haan , linux-kernel@vger.kernel.org, Hans de Goede , linux-sunxi@googlegroups.com, Jens Kuske , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] clk: sunxi: Extend the simple gates and handle the Allwinner H3 Message-ID: <20151207143102.GA29097@rob-hp-laptop> References: <20151206100412.1a74b71da8e9ca28c6e61589@free.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20151206100412.1a74b71da8e9ca28c6e61589@free.fr> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2317 Lines: 51 On Sun, Dec 06, 2015 at 10:04:12AM +0100, Jean-Francois Moine wrote: > The H3 has a clock gate definition similar to the other Allwinner SoCs, > but with a different parent clock for each single gate. > > Adding the names of the parent clocks in both the source and output clocks > permits the use of the simple-gates driver to define the bus gates > of all known Allwinner SoCs. > > Signed-off-by: Jean-Francois Moine > --- > This patch replaces a part of Jens Kuske's patch > [PATCH v5 1/4] clk: sunxi: Add H3 clocks support > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 25 +++++++++++++++++++++++ > drivers/clk/sunxi/clk-simple-gates.c | 14 ++++++++++++- > 2 files changed, 38 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index 8a47b77..5736e6d 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -70,6 +70,7 @@ Required properties: > "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 > "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 > "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 > + "allwinner,sunxi-gates-clk" - simple gates > > Required properties for all clocks: > - reg : shall be the control register address for the clock. > @@ -93,6 +94,12 @@ The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: > - #reset-cells : shall be set to 1 > - resets : shall be the reset control phandle for the mmc block. > > +The "allwinner,sunxi-gates-clk" clock also requires: > +- clock-names : corresponding names of the parent clocks > +when the output clocks have different parents. > +These names must be 4 characters long and must appear as a prefix in > +the names of the output clocks. See example. > + I don't think you should be encoding relationships of clocks using the name strings. We describe relationships in DT via parent/child or phandles. Rob -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/