Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933133AbbLHJUA (ORCPT ); Tue, 8 Dec 2015 04:20:00 -0500 Received: from smtp5-g21.free.fr ([212.27.42.5]:4923 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932423AbbLHJT4 convert rfc822-to-8bit (ORCPT ); Tue, 8 Dec 2015 04:19:56 -0500 Date: Tue, 8 Dec 2015 10:19:49 +0100 From: Jean-Francois Moine To: Maxime Ripard Cc: Jens Kuske , Chen-Yu Tsai , Rob Herring , Michael Turquette , Stephen Boyd , Linus Walleij , devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?ISO-8859-1?Q?L=F3pez?= , Reinder de Haan , linux-kernel@vger.kernel.org, Hans de Goede , linux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-Id: <20151208101949.4c596117eb3b6b4551dd0cea@free.fr> In-Reply-To: <20151208083224.GN27957@lukather> References: <1449264283-25360-1-git-send-email-jenskuske@gmail.com> <1449264283-25360-4-git-send-email-jenskuske@gmail.com> <20151207091257.070723b67db726d9f05c6550@free.fr> <5665D38E.4050406@gmail.com> <20151208090658.e471fcde7fd5e79c69706115@free.fr> <20151208083224.GN27957@lukather> X-Mailer: Sylpheed 3.4.3 (GTK+ 2.24.28; armv7l-unknown-linux-gnueabihf) Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1307 Lines: 32 On Tue, 8 Dec 2015 09:32:24 +0100 Maxime Ripard wrote: > If the H3 display block is done the same way than the A10 (and later) > one on this aspect, then the TCON has two channels with two different > streaming (or functional, you pick the name) clocks. The channel 0 is > usually used for RGB, the channel 1 for HDMI, composite and VGA. > > Maybe they just added different bus gates for those two different > channels, and moved HDMI to the channel 0. > > Anyway, that can always be changed later on if we have more clue on > what's going on. I don't know about the other Allwinner chips, and your DRM driver for these ones cannot be reused for the H3 because its display engine (DE.2) is completely different. The DE2 runs at 432MHz and treats both LCDs. The TCON1 runs at a fixed rate, 200MHz, and the streaming rates are defined by the HDMI (LCD0) and TCON0 (LCD1) clocks. BTW, I hope to submit a H3 DRM driver before new year. -- Ken ar c'henta? | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/