Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754749AbbLIK3v (ORCPT ); Wed, 9 Dec 2015 05:29:51 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:35995 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754622AbbLIK3o (ORCPT ); Wed, 9 Dec 2015 05:29:44 -0500 Subject: Re: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region To: Arnd Bergmann , Pratyush Anand References: <1449149725-27607-1-git-send-email-stanimir.varbanov@linaro.org> <56669C50.9060700@linaro.org> <1975309.Hla8QhEqf4@wuerfel> Cc: Stanimir Varbanov , Russell King - ARM Linux , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , Bjorn Helgaas , Jingoo Han , Srinivas Kandagatla , Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Bjorn Andersson From: Stanimir Varbanov Message-ID: <56680292.60905@linaro.org> Date: Wed, 9 Dec 2015 12:29:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1975309.Hla8QhEqf4@wuerfel> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2441 Lines: 57 On 12/09/2015 11:52 AM, Arnd Bergmann wrote: > On Wednesday 09 December 2015 10:10:05 Pratyush Anand wrote: >> On Tue, Dec 8, 2015 at 2:31 PM, Stanimir Varbanov >>>> Signed-off-by: Stanimir Varbanov >>>> --- >>>> drivers/pci/host/pcie-designware.c | 5 +++++ >>>> 1 file changed, 5 insertions(+) >>>> >>>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c >>>> index 02a7452bdf23..ed4dc2e2553b 100644 >>>> --- a/drivers/pci/host/pcie-designware.c >>>> +++ b/drivers/pci/host/pcie-designware.c >>>> @@ -164,6 +164,11 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, >>>> dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); >>>> dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); >>>> dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); >>>> + /* >>>> + * ensure that the ATU enable has been happaned before accessing >>>> + * pci configuration/io spaces through dw_pcie_cfg_[read|write]. >>>> + */ >>>> + wmb(); >>>> } >>>> >> >> >> My understnading is that since writel() of dw_pcie_writel_rc() in >> above code and readl(), writel() of dw_pcie_cfg_[read|write]() (which >> will follow) goes through same device (ie PCIe host here). So, it is >> guaranteed that 1st writel() will be executed before later >> readl()/writel(). If that is true then we do not need any explicit >> barrier here. >> >> Arnd, Russel: whats your opinion here. > > I think the ordering is only enforced if the two register accesses are > on the same device as seen from the bus, and it's possible that the > RC registers and the config space registers are not considered the > same thing here. > > For config write, this is not a problem, because the config space write > has a wmb() that enforces ordering, but it's possible that the config > space read may hit the device in parallel with the PCIE_ATU_ENABLE > write. Hmm, just a matter of fact - as I described in the patch description this wmb() fixed an issue with pcie device enumeration (I came down to pci_bus_read_dev_vendor_id() returns zero) i.e. exactly a pci configuration space read. -- regards, Stan -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/