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Date: Wed, 9 Dec 2015 18:30:01 -0800
From: Brian Norris <computersforpeace@gmail.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Simon Arlott <simon@fire.lp0.eu>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        David Woodhouse <dwmw2@infradead.org>, linux-mtd@lists.infradead.org,
        Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Kumar Gala <galak@codeaurora.org>,
        bcm-kernel-feedback-list@broadcom.com,
        Kamal Dasu <kdasu.kdev@gmail.com>, Jonas Gorski <jogo@openwrt.org>
Subject: Re: [PATCH linux-next (v2) 1/3] mtd: brcmnand: Add brcm,bcm6368-nand
 device tree binding
Message-ID: <20151210023001.GI144338@google.com>
References: <566891DA.1050208@simon.arlott.org.uk>
 <566896B6.9010204@gmail.com>
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On Wed, Dec 09, 2015 at 01:01:42PM -0800, Florian Fainelli wrote:
> Le 09/12/2015 12:40, Simon Arlott a ?crit :
> > Add device tree binding for NAND on the BCM6368.
> > 
> > The BCM6368 has a NAND interrupt register with combined status and enable
> > registers. It also requires a clock, so add an optional clock to the
> > common brcmnand binding.
> > 
> 
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

Applied this and patches 2 and 3 to l2-mtd.git, with one small fix,
below.

> > Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
> > ---
> > Changed "nand-intr-base" reg name to "nand-int-base".
> > 
> >  .../devicetree/bindings/mtd/brcm,brcmnand.txt      | 32 ++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> > index 4ff7128..ebfa6fc 100644
> > --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> > +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> > @@ -45,6 +45,8 @@ Required properties:
> >  - #size-cells      : <0>
> >  
> >  Optional properties:
> > +- clock                     : reference to the clock for the NAND controller
> > +- clock-names               : "nand" (required for the above clock)
> >  - brcm,nand-has-wp          : Some versions of this IP include a write-protect
> >                                (WP) control bit. It is always available on >=
> >                                v7.0. Use this property to describe the rare
> > @@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w
> >         and enable registers
> >       - reg-names: (required) "nand-int-base"
> >  
> > +   * "brcm,nand-bcm6368"
> > +     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
> > +     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
> > +       and enable registers, and boot address registers
> > +     - reg-names: (required) "nand-int-base"
> > +
> >     * "brcm,nand-iproc"
> >       - reg: (required) the "IDM" register range, for interrupt enable and APB
> >         bus access endianness configuration, and the "EXT" register range,
> > @@ -148,3 +156,27 @@ nand@f0442800 {
> >  		};
> >  	};
> >  };
> > +
> > +nand@10000200 {
> > +	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
> > +		"brcm,brcmnand-v4.0", "brcm,brcmnand";
> > +	reg = <0x10000200 0x180>,
> > +	      <0x10000600 0x200>,
> > +	      <0x100000b0 0x10>;
> > +	reg-names = "nand", "nand-cache", "nand-intr-base";

s/intr/int/

> > +	interrupt-parent = <&periph_intc>;
> > +	interrupts = <50>;
> > +	clocks = <&periph_clk 20>;
> > +	clock-names = "nand";
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +
> > +	nand0: nandcs@0 {
> > +		compatible = "brcm,nandcs";
> > +		reg = <0>;
> > +		nand-on-flash-bbt;
> > +		nand-ecc-strength = <1>;
> > +		nand-ecc-step-size = <512>;
> > +	};
> > +};
> > 
> 
> 
> -- 
> Florian
--
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