Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752613AbbLJLgG (ORCPT ); Thu, 10 Dec 2015 06:36:06 -0500 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:40769 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750820AbbLJLgE (ORCPT ); Thu, 10 Dec 2015 06:36:04 -0500 Date: Thu, 10 Dec 2015 11:35:41 +0000 From: Mark Brown To: Jon Hunter Cc: Arnd Bergmann , linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Viresh Kumar , Stephen Warren , Thierry Reding , Alexandre Courbot , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Liam Girdwood Message-ID: <20151210113541.GL5727@sirena.org.uk> References: <2194927.eV2s2QmZs0@wuerfel> <5668188F.2080202@nvidia.com> <20151209144734.GB5727@sirena.org.uk> <566865ED.3020106@nvidia.com> <20151209201007.GG5727@sirena.org.uk> <56694EFA.7010901@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="3VH1SAMC12vKu3aE" Content-Disposition: inline In-Reply-To: <56694EFA.7010901@nvidia.com> X-Cookie: revolutionary, adj.: User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH] cpufreq: tegra: add regulator dependency for T124 X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2336 Lines: 55 --3VH1SAMC12vKu3aE Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Dec 10, 2015 at 10:07:54AM +0000, Jon Hunter wrote: > On 09/12/15 20:10, Mark Brown wrote: > > On Wed, Dec 09, 2015 at 05:33:33PM +0000, Jon Hunter wrote: > >> Yes, setting the frequency and voltage as defined by a given operating > >> mode would make sense. However, I am not sure we have those defined in > >> the kernel for this PLL and would have to be added. > > I think given how you're describing the hardware that this will be > > required in order to provide something robust (and also to get the best > > power savings from the hardware). > Yes I agree it would be more robust. However, if you care about power > savings then you should be using the DFLL/cpufreq anyway. Without knowing anything about the hardware this is all a bit confusing I'm afraid. What is "DFLL/cpufreq" as opposed to "the PLL"? > From testing the t124 jetson and nyan-big, both of these boards have a > different configuration for the PLL at boot time, so although we could > pick a safe operating point for all t124 boards, I was thinking of just > restoring their initial configuration. This seems more complex, and also makes the idea of relying on the initial configuration seem slightly concerning - other software seems to be already changing the configuration before we get to the kernel so if we don't fully understand the configuration we're doing we seem likely to find some configuration where we miss things. --3VH1SAMC12vKu3aE Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJWaWOMAAoJECTWi3JdVIfQMJkH/i6uPUSyCZIzPffFPthJw2Vb KpVwq2s8OdpX82UNG/m4Yd7lH7GrVvixdAVnBtI6tR9HO3wBI/2eCCcBSXX0H7WT JmxqXK5Yk6Vqi6JmKppecQk1PtYhli7alaIOobvI4GjCplEnQIH9Ky+4O27wIQS2 Pg0JZp53Q0QqqVUYc+S6hmCId1SYqmNC14WO3kCK7y/NFwc+hanpVE1iAM5U6w4e jMwl2ZYXGMYSwBOf7SwfGQMk/ioHnfo5u9lQCFYqLJNz0srdVFjf7nOCFg4/NW4r klWrVgJ7Bb3Vo8FFTITap8FApD7OPnVO8DS4T4WqQKMVRlbzlPFqBXhgLvI/Xso= =Eiwj -----END PGP SIGNATURE----- --3VH1SAMC12vKu3aE-- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/