Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753770AbbLPLoJ (ORCPT ); Wed, 16 Dec 2015 06:44:09 -0500 Received: from mail-wm0-f48.google.com ([74.125.82.48]:37910 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752217AbbLPLoG convert rfc822-to-8bit (ORCPT ); Wed, 16 Dec 2015 06:44:06 -0500 Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 9.2 \(3112\)) Subject: Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock From: "Ivan T. Ivanov" In-Reply-To: Date: Wed, 16 Dec 2015 13:44:01 +0200 Cc: Stephen Boyd , Bjorn Andersson , Georgi Djakov , Bjorn Andersson , Peter Griffin , linux-mmc , "linux-kernel@vger.kernel.org" , linux-arm-msm Content-Transfer-Encoding: 8BIT Message-Id: <942B071D-D7F6-4D20-916C-BBE9096146E9@linaro.org> References: <1436183618-15330-1-git-send-email-ivan.ivanov@linaro.org> <20151106233913.GB30882@usrtlx11787.corpusers.net> <20151110201841.GB24116@codeaurora.org> To: Ulf Hansson X-Mailer: Apple Mail (2.3112) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2445 Lines: 60 > On Dec 16, 2015, at 12:18 PM, Ulf Hansson wrote: > > [...] > >>> It seems like a reasonable assumption that the controller can't cope >>> with a higher clock rate than 100 MHz as "input" clock. That would >>> then mean that there are different versions of the controller, as it >>> seems like for some version it's fine with 200MHz and for some 100MHz. >>> >>> According to the DT compatible strings, *one* version is currently >>> supported, "qcom,sdhci-msm-v4"... >> >> The same version of hardware is there 4 times. The difference is >> the maximum clock frequency supported by them is different. In >> downstream kernels we've handled this by trimming the frequency >> tables for the different controllers in the clock driver. >> Setting the clock to INT_MAX will make it run at 400MHz, which >> doesn't look to be supported by anything besides sdc1 on 8974ac. >> >>> >>> I see two viable solutions. One would be to limit the clock rate >>> depending on the version of the controller (new compatible strings >>> needs to be added). Another one would be to limit the clock rate by >>> using the existing DT binding for max-frequency, and thus do a >>> clk_set_rate(mmc->f_max) during probe. >>> >> >> I'd rather see that done via OPP tables in DT, but I suppose >> max-frequency is fine too. We'll need to use OPPs soon enough >> because there's a voltage associated with that frequency. >> >> In case you're wondering, the max frequency for sdc1 on 8974ac is >> 400MHz. If it's just a plain 8974pro then the max frequency is >> 200MHz. Otherwise, sdc2 maxes out at 200Mhz and sdc3 and sdc4 max >> out at 100MHz. >> > > I think we have reached a consensus on the viable options. > > As we haven't heard from Ivan, do someone want to send a patch for > this or shall we just revert $subject patch (which I can deal with)? I am following this discussion, but I am not sure what I could do. If my understanding is correct, even if controllers report same version, they don’t support 400MHz core clock. Initial patch fixes real issue. I am voting for “max-frequency” DT property. I don’t have 8974ac, so I can not test the change. Regards, Ivan -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/