Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965034AbbLRRpe (ORCPT ); Fri, 18 Dec 2015 12:45:34 -0500 Received: from resqmta-ch2-02v.sys.comcast.net ([69.252.207.34]:57941 "EHLO resqmta-ch2-02v.sys.comcast.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932091AbbLRRpb (ORCPT ); Fri, 18 Dec 2015 12:45:31 -0500 Date: Fri, 18 Dec 2015 11:45:29 -0600 (CST) From: Christoph Lameter X-X-Sender: cl@east.gentwo.org To: Fenghua Yu cc: "H. Peter Anvin" , Ingo Molnar , Thomas Gleixner , Tony Luck , Ravi V Shankar , Peter Zijlstra , Tejun Heo , Marcelo Tosatti , linux-kernel , x86 Subject: Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support In-Reply-To: <1450392376-6397-1-git-send-email-fenghua.yu@intel.com> Message-ID: References: <1450392376-6397-1-git-send-email-fenghua.yu@intel.com> Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1522 Lines: 34 On Thu, 17 Dec 2015, Fenghua Yu wrote: > Intel Cache allocation support: > > Cache allocation patches adds a cgroup subsystem to support the new > Cache Allocation feature found in future Intel Xeon Intel processors. > Cache Allocation is a sub-feature with in Resource Director > Technology(RDT) feature. Current patches support only L3 cache > allocation. > > Cache Allocation provides a way for the Software (OS/VMM) to restrict > cache allocation to a defined 'subset' of cache which may be overlapping > with other 'subsets'. This feature is used when a thread is allocating > a cache line ie when pulling new data into the cache. > > Threads are associated with a CLOS(Class of service). OS specifies the > CLOS of a thread by writing the IA32_PQR_ASSOC MSR during context > switch. The cache capacity associated with CLOS 'n' is specified by > writing to the IA32_L3_MASK_n MSR. Could you also support another low level interface where a task (or process) can set the CLOS id itself if it has CAP_SYS_NICE. Plus some way for the supervisor to directly control the IA32_L3_MASK_n MSR? Is there a way to see these values for debugging purposes? We tightly control processes and bind them to processors. cpusets are often a too high level instrument at that level. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/