Message-ID: <1450724880.30729.250.camel@linux.intel.com>
Subject: Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find
 dma channel
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: =?ISO-8859-1?Q?M=E5ns_Rullg=E5rd?= <mans@mansr.com>,
        Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Julian Margetson <runaway@candw.ms>, Tejun Heo <tj@kernel.org>,
        linux-ide@vger.kernel.org,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Date: Mon, 21 Dec 2015 21:08:00 +0200
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Organization: Intel Finland Oy
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On Mon, 2015-12-21 at 01:19 +0000, Måns Rullgård wrote:
> Andy Shevchenko <andy.shevchenko@gmail.com> writes:
> 
> > P.S. I also noticed that original driver enables interrupt per each
> > block
> 
> And then ignores all but the transfer complete interrupt.
> 
> > and sets protection control bits.
> 
> With no indication what the value it sets is supposed to mean.

Okay, let's summarize what we have:

0. AR: Get a working reference for PPC 460EX SATA driver
1. AR: Clear LLP_EN bits at the last block of LLP transfer
2. AR: Rename masters to 'memory' and 'peripheral' and change them per
DMA direction
3. AR: Set LMS (LLP master) to 'memory' when do LLP transfers
4. CHECK: PROTCTL bit (documentation says that recommended value is
0x01)
5. CHECK: Other bits in CFG register (FIFO_MODE, FCMODE)
6. CHECK: Block interrupts vs. one interrupt at the end of block chain
(Måns, I missed how any of them is ignored)
7. AR: Test everything on Intel SoCs such as Baytrail, CherryTrail, etc
(SPI, UART, dmatest), AVR32 (MMC, dmatest), PPC 460EX (Onboard SATA)


I can share my working branch with a set of patches regarding to
dw_dmac. We may do our work based on that code and after I'll submit
everything to upstream. Does it sound okay for you, guys?

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

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