Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753108AbcCALDZ (ORCPT ); Tue, 1 Mar 2016 06:03:25 -0500 Received: from mail-db3on0057.outbound.protection.outlook.com ([157.55.234.57]:7262 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751976AbcCALDX (ORCPT ); Tue, 1 Mar 2016 06:03:23 -0500 From: Minghuan Lian To: Marc Zyngier , "linux-arm-kernel@lists.infradead.org" CC: Thomas Gleixner , Jason Cooper , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH 2/2 v3] irqchip/Layerscape: Add SCFG MSI controller support Thread-Topic: [PATCH 2/2 v3] irqchip/Layerscape: Add SCFG MSI controller support Thread-Index: AQHRXZgScr2rNDogoEG2P31zW/fLGZ8wlnaAgAufZ6CABsLkAIABCcLQ Date: Tue, 1 Mar 2016 11:03:18 +0000 Message-ID: References: <1454403648-5551-1-git-send-email-Minghuan.Lian@nxp.com> <1454403648-5551-2-git-send-email-Minghuan.Lian@nxp.com> <56C4AE17.4050301@arm.com> <56D41A04.8030302@arm.com> In-Reply-To: <56D41A04.8030302@arm.com> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [199.59.226.141] x-microsoft-exchange-diagnostics: 1;VI1PR04MB1022;5:7PtL3Fm+ci94652IPB1TbF5Qld1/m3lMG7jzur2EPiOnGwngg9XuCPR1Zh6KXUgssPGF5D7RAaK9fv+yppEerfXm4Pi91cw1HW55KkcOKVP1qd5bIyBWkxJJ7T/aHHcyEYkyVX6m/LPQoLtWsoC2qw==;24:lKa32sbA8AJRpTRcmL83oObWU9u9m1nQERhXJ9fcvIIMo1hfcGWxsLnXOKzthnn9IHZqfiyQjeUba8+kNrQTP+ShJSMpCOSTW3jzbYMRFxY= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:VI1PR04MB1022; x-ms-office365-filtering-correlation-id: b19bb9f0-2a10-4a0c-eb6e-08d341c11893 x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001);SRVR:VI1PR04MB1022;BCL:0;PCL:0;RULEID:;SRVR:VI1PR04MB1022; x-forefront-prvs: 086831DFB4 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(24454002)(479174004)(45984002)(377454003)(13464003)(52314003)(164054003)(19580395003)(92566002)(3846002)(66066001)(10400500002)(19580405001)(77096005)(86362001)(40100003)(33656002)(54356999)(76176999)(2900100001)(81156008)(2950100001)(50986999)(5004730100002)(3280700002)(2906002)(2501003)(1096002)(4326007)(189998001)(74316001)(5003600100002)(102836003)(5002640100001)(5001770100001)(93886004)(76576001)(106116001)(1220700001)(6116002)(87936001)(5008740100001)(3660700001)(122556002)(586003)(5001960100003)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR04MB1022;H:VI1PR04MB1615.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Mar 2016 11:03:18.2931 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1022 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u21B3Uv9031167 Content-Length: 2643 Lines: 79 Hi Marc, Please see my comments inline. Thanks, Minghaun > -----Original Message----- > From: Marc Zyngier [mailto:marc.zyngier@arm.com] > Sent: Monday, February 29, 2016 6:14 PM > To: Minghuan Lian ; > linux-arm-kernel@lists.infradead.org > Cc: Thomas Gleixner ; Jason Cooper > ; Roy Zang ; Mingkai Hu > ; Stuart Yoder ; Yang-Leo Li > ; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/2 v3] irqchip/Layerscape: Add SCFG MSI controller > support > > On 25/02/16 03:21, Minghuan Lian wrote: > > Hi Marc, > > > > I am sorry for the delayed response due to the Chinese Spring Festival holiday. > > Thank you very much for the review. > > Please see my comments inline. > > > > Thanks, > > Minghuan > > > > [...] > > >>> +static int ls_scfg_msi_probe(struct platform_device *pdev) { > >>> + struct ls_scfg_msi *msi_data; > >>> + struct resource *res; > >>> + int ret; > >>> + > >>> + msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), > GFP_KERNEL); > >>> + if (!msi_data) > >>> + return -ENOMEM; > >>> + > >>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > >>> + msi_data->regs = devm_ioremap_resource(&pdev->dev, res); > >>> + if (IS_ERR(msi_data->regs)) { > >>> + dev_err(&pdev->dev, "failed to initialize 'regs'\n"); > >>> + return PTR_ERR(msi_data->regs); > >>> + } > >>> + msi_data->msiir_addr = res->start; > >>> + > >>> + msi_data->irq = platform_get_irq(pdev, 0); > >>> + if (msi_data->irq <= 0) { > >>> + dev_err(&pdev->dev, "failed to get MSI irq\n"); > >>> + return -ENODEV; > >>> + } > >>> + > >>> + msi_data->pdev = pdev; > >>> + msi_data->nr_irqs = MSI_MAX_IRQS; > >> > >> So this is hardcoded, always. Why do you need a nr_irqs variable at all? > > [Lian Minghuan-B31939] Currently, nr_irqs is always 32, but in the > > future, the MSI controller may be extended to support more IRQs. And, > > we may set nr_irqs the value of less than 32 to reserve some IRQs for > > special usage. So nr_irqs can bring flexibility > > You have to choose: either this is configurable and you describe it in > DT, or this is not and you drop this field from the structure. > > As for the "reserved interrupts", that would need to be described too. > [Minghuan Lian] I will drop this field in next version. The old version of LS1021a only supports one MSI interrupt. So the driver needs to change nr_irq to 1. Anyway, this issue has been fixed. Now, all the Layerscape SoC supports 32 MSI interrupts. > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...