Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752262AbcCARmx (ORCPT ); Tue, 1 Mar 2016 12:42:53 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5219 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750997AbcCARmw (ORCPT ); Tue, 1 Mar 2016 12:42:52 -0500 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 01 Mar 2016 09:41:39 -0800 Date: Tue, 1 Mar 2016 18:42:36 +0100 From: Thierry Reding To: Laxman Dewangan CC: Arnd Bergmann , , , , , , Rhyland Klein Subject: Re: [PATCH 1/1] arm64: defconfig: Enable Maxim PMIC max77620 config Message-ID: <20160301174235.GA30025@ulmo.nvidia.com> References: <1456750972-13972-1-git-send-email-ldewangan@nvidia.com> <3235756.j5eVi1g2v0@wuerfel> <56D57EF3.6060805@nvidia.com> MIME-Version: 1.0 In-Reply-To: <56D57EF3.6060805@nvidia.com> X-NVConfidentiality: public User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.2.69.134] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL102.nvidia.com (10.26.138.15) Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0F1p//8PRICkK4MW" Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2675 Lines: 71 --0F1p//8PRICkK4MW Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 01, 2016 at 05:07:23PM +0530, Laxman Dewangan wrote: >=20 > On Tuesday 01 March 2016 05:02 AM, Arnd Bergmann wrote: > >On Monday 29 February 2016 18:32:52 Laxman Dewangan wrote: > >>Enable following configs for the Maxim Semiconductor's PMIC > >>MAX77620/MAX20024. This is used on NVIDIA's Tegra 210 platform > >>Jetson-TX1. > >> > >> CONFIG_MFD_MAX77620 For MFD driver. > >> CONFIG_PINCTRL_MAX77620 For pin control support > >> CONFIG_GPIO_MAX77620 for GPIO Support. > >> CONFIG_REGULATOR_MAX77620 for regulator support. > >> CONFIG_RTC_DRV_MAX77686 for RTC support. > >> > >>Enable Tegra I2C config to enable I2C in NVIDIA's Tegra 210 > >>platforms. > >> > >>Signed-off-by: Laxman Dewangan > >>--- > >>The patches for drivers of MFD/GPIO/Pincontrol are in flight. > >> > >I'm not entirely sure what you had meant to happen to this patch, > >as you have a lot of people in the 'To' line. > > > >Do you want us to pick it up into arm-soc with Thierry's Ack, > >or should he forward it, or is there a reason for Catalin and > >Will to put it into the arm64 tree? > > > > >=20 > Not sure how will it go (via Tegra or arm-soc) but I will need Thierry's = or > Rhyland Klein's ACK. I'd prefer to take this through the Tegra tree. I'll probably postpone that until after v4.6 and merge this as the drivers get merged and after they can be enabled and verified on the Jetson TX1. Laxman, generally the defconfig changes go in through platform trees, so please send those to me in the future. I'll make sure to forward those to arm-soc with the rest of the Tegra patches. Thierry --0F1p//8PRICkK4MW Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJW1dSHAAoJEN0jrNd/PrOhQ5AP/0+ur+D7uORHtfKCVtW6YhCu FsIpvQ7VUq27dxYI5hrDQfqQM+bx8Nuj1YjXhLOn8Wz0wzbGjlPqYViuNx16wMLf iiNyo4Fg8/bpR9vtTlWOtg41ZLnJI31AH3G8kYuuc65Dnnu/ID30g8MkaIWWbIxo K4kMdlvD9O7YjcKRTS2NoG3ovPD4ppgG06wwstsW6LtZ677AXyDVTkYDCg1eybvl RZLnN0oO4RV5CIbZvjPuxV6T7GJlEiY0A20aYo1yCgm4O4ysrGGBYZ0Pyry4hngO DGOihwErZYNfzSDqGbyMaklz86MzhNMTXbHYjH/8h7IdygJkR9nTMu2HActt5h4f 4xdMtMD5gqjen0NR/rk+ZFH9b0MNLj55cg/ckLIxLDkOuhEmvaqxY9H1BGUTpLQg UEZ3AjiIJTZlAJ+KZTR30BDEMKsJP9ttuh801vbGAS/CwoiUO32hfLxAgYPS9cQ8 t4tGvlE4kfDwIiBNMvXzdpj3HUMs8NrKDZLAUom8VM91jNYIjfzO4KV0XNDJ+wYM +y7NDQXeeB31/00WRwZp2LzDeEQgSIwqQU/eKRpCf2a9NgqCetSYSTrBtzNZWJAE fL+RMtbY84rYav3bePVzUXn4g0FJptG2lFccHVmM1SvUKe860wgiUbBa6QwbUCis yuNbAHGcFpcoQ6bWJ4QA =hwDk -----END PGP SIGNATURE----- --0F1p//8PRICkK4MW--