Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755569AbcCBSZa (ORCPT ); Wed, 2 Mar 2016 13:25:30 -0500 Received: from mail-ig0-f196.google.com ([209.85.213.196]:32967 "EHLO mail-ig0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750898AbcCBSZ2 (ORCPT ); Wed, 2 Mar 2016 13:25:28 -0500 MIME-Version: 1.0 In-Reply-To: <20160302181314.GA25030@rob-hp-laptop> References: <1456437887-24432-1-git-send-email-manabian@gmail.com> <1456437887-24432-3-git-send-email-manabian@gmail.com> <20160302181314.GA25030@rob-hp-laptop> Date: Wed, 2 Mar 2016 19:25:27 +0100 Message-ID: Subject: Re: [PATCH 2/2] devicetree: document NXP LPC1850 PINT irq controller binding From: Joachim Eastwood To: Rob Herring Cc: Thomas Gleixner , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , devicetree@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1795 Lines: 43 On 2 March 2016 at 19:13, Rob Herring wrote: > On Thu, Feb 25, 2016 at 11:04:47PM +0100, Joachim Eastwood wrote: >> Add binding documentation for NXP LPC1850 GPIO Pin Interrupt (PINT) >> controller. >> >> Signed-off-by: Joachim Eastwood >> --- >> .../interrupt-controller/nxp,lpc1850-gpio-pint.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc1850-gpio-pint.txt >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc1850-gpio-pint.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc1850-gpio-pint.txt >> new file mode 100644 >> index 000000000000..dc43f187ebda >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc1850-gpio-pint.txt >> @@ -0,0 +1,22 @@ >> +NXP LPC18xx/43xx GPIO Pin Interrupt (PINT) controller >> + >> +Required properties: >> + >> +- compatible : should be "nxp,lpc1850-gpio-pint". >> +- reg : Specifies base physical address and size of the registers. >> +- interrupt-controller : Identifies the node as an interrupt controller >> +- #interrupt-cells : Specifies the number of cells needed to encode an >> + interrupt source. The value shall be 2. >> +- interrupts : Specifies the CPU interrupts the controller is connected to. > > How many (8?) and what's the ordering? The PINT on has 8 interrupts, but this is device dependent. Up to 32 could be supported. The order is also device dependent. The interrupts on PINT are merely mapped onto the main interrupt controller. I tried to keep the wording in the binding generic so it could support the PINT on different devices. I'll update the text with some more details. regards, Joachim Eastwood