Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756365AbcCCLvr (ORCPT ); Thu, 3 Mar 2016 06:51:47 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:35334 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755680AbcCCLkj (ORCPT ); Thu, 3 Mar 2016 06:40:39 -0500 From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Neil Armstrong Subject: [PATCH 09/17] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Date: Thu, 3 Mar 2016 12:40:02 +0100 Message-Id: <1457005210-18485-10-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1248 Lines: 38 Signed-off-by: Neil Armstrong --- .../devicetree/bindings/clock/plxtech,stdclk.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/plxtech,stdclk.txt diff --git a/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt b/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt new file mode 100644 index 0000000..46465c6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt @@ -0,0 +1,24 @@ +PLX Technology OXNAS SoC Family Standard Clocks +================================================ + +Please also refer to clock-bindings.txt in this directory for common clock +bindings usage. + +Required properties: +- compatible: Should be "plxtech,ox810se-stdclk" or "plxtech,nas782x-stdclk" +- #clock-cells: 1, see below + +Parent node should have the following properties : +- compatible: Should be "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd" + +example: + +sys: sys-ctrl@000000 { + compatible = "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + stdclk: stdclk { + compatible = "plxtech,ox810se-stdclk", "plxtech,nas782x-stdclk"; + #reset-cells = <1>; + }; +}; -- 1.9.1