Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757750AbcCCNkp (ORCPT ); Thu, 3 Mar 2016 08:40:45 -0500 Received: from mailout.micron.com ([137.201.242.129]:27313 "EHLO mailout.micron.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757695AbcCCNkl (ORCPT ); Thu, 3 Mar 2016 08:40:41 -0500 From: =?gb2312?B?QmVhbiBIdW8gu/Sx87HzIChiZWFuaHVvKQ==?= To: Yunhui Cui CC: "linux-mtd@lists.infradead.org" , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "han.xu@freescale.com" , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , "yao.yuan@nxp.com" , "yunhui.cui@nxp.com" Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Thread-Topic: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Thread-Index: AdF1UHMSvUm18pViRPuUX1gTcWBaOg== Date: Thu, 3 Mar 2016 13:39:29 +0000 Message-ID: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.167.84.5] X-TM-AS-Product-Ver: SMEX-11.0.0.4255-8.000.1202-22168.003 X-TM-AS-Result: No--6.761100-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No x-mt-checkinternalsenderrule: True Content-Type: text/plain; charset="gb2312" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u23DeoUw023165 Content-Length: 1820 Lines: 55 > From: Yunhui Cui > To: , , > > Cc: , , > , , Yunhui > Cui > > Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW > protection > Message-ID: <1456988044-37061-4-git-send-email-B56489@freescale.com> > Content-Type: text/plain > > From: Yunhui Cui > > For Micron family ,The status register write enable/disable bit, provides > hardware data protection for the device. > When the enable/disable bit is set to 1, the status register nonvolatile bits > become read-only and the WRITE STATUS REGISTER operation will not > execute. > > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index ed0c19c..917f814 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -39,6 +39,7 @@ > > #define SPI_NOR_MAX_ID_LEN 6 > #define SPI_NOR_MAX_ADDR_WIDTH 4 > +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f > > struct flash_info { > char *name; > @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, enum read_mode mode) > write_sr(nor, 0); > } > > + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { > + ret = read_sr(nor); > + ret &= SPI_NOR_MICRON_WRITE_ENABLE; > + For Micron the status register write enable/disable bit, its default/factory value is disable. Can here first check ,then program? > + write_enable(nor); > + write_sr(nor, ret); > + } > + > if (!mtd->name) > mtd->name = dev_name(dev); > mtd->priv = nor;