From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
To: <bp@alien8.de>, <tony.luck@intel.com>, <hpa@zytor.com>, <mingo@redhat.com>,
        <tglx@linutronix.de>, <dougthompson@xmission.com>,
        <mchehab@osg.samsung.com>
CC: <x86@kernel.org>, <linux-edac@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <ashok.raj@intel.com>,
        <gong.chen@linux.intel.com>, <len.brown@intel.com>,
        <peterz@infradead.org>, <ak@linux.intel.com>,
        <alexander.shishkin@linux.intel.com>, <Yazen.Ghannam@amd.com>
Subject: [PATCH V3 4/5] x86/mce: Clarify comments regarding deferred error
Date: Thu, 3 Mar 2016 10:10:57 -0600
Message-ID: <1457021458-2522-5-git-send-email-Aravind.Gopalakrishnan@amd.com>
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References: <1457021458-2522-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
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The Deferred field indicates if we have a Deferred error.
Deferred errors indicate errors that hardware could not
fix. But it still does not cause any interruption to program
flow. So it does not generate any #MC and UC bit in MCx_STATUS
is not set.

Fixing comment here. No functional change

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/include/asm/mce.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0681d0a..b016219 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7 +40,7 @@
 #define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */
 
 /* AMD-specific bits */
-#define MCI_STATUS_DEFERRED	(1ULL<<44)  /* declare an uncorrected error */
+#define MCI_STATUS_DEFERRED	(1ULL<<44)  /* uncorrected error, deferred exception */
 #define MCI_STATUS_POISON	(1ULL<<43)  /* access poisonous data */
 #define MCI_STATUS_TCC		(1ULL<<55)  /* Task context corrupt */
 
-- 
2.7.0