From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
To: <bp@alien8.de>, <tony.luck@intel.com>, <hpa@zytor.com>, <mingo@redhat.com>,
        <tglx@linutronix.de>, <dougthompson@xmission.com>,
        <mchehab@osg.samsung.com>
CC: <x86@kernel.org>, <linux-edac@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <ashok.raj@intel.com>,
        <gong.chen@linux.intel.com>, <len.brown@intel.com>,
        <peterz@infradead.org>, <ak@linux.intel.com>,
        <alexander.shishkin@linux.intel.com>, <Yazen.Ghannam@amd.com>
Subject: [PATCH V3 5/5] x86/mce/AMD: Add comments for easier understanding
Date: Thu, 3 Mar 2016 10:10:58 -0600
Message-ID: <1457021458-2522-6-git-send-email-Aravind.Gopalakrishnan@amd.com>
In-Reply-To: <1457021458-2522-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
References: <1457021458-2522-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
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In an attempt to aid in understanding of what the threshold_block
structure holds, provide comments to describe the members here.
Also, trim comments around threshold_restart_bank()
and update copyright info.

No functional change is introduced.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/include/asm/amd_nb.h        | 18 +++++++++---------
 arch/x86/kernel/cpu/mcheck/mce_amd.c |  7 ++-----
 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 3c56ef1..bc01c0a 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -27,15 +27,15 @@ struct amd_l3_cache {
 };
 
 struct threshold_block {
-	unsigned int		block;
-	unsigned int		bank;
-	unsigned int		cpu;
-	u32			address;
-	u16			interrupt_enable;
-	bool			interrupt_capable;
-	u16			threshold_limit;
-	struct kobject		kobj;
-	struct list_head	miscj;
+	unsigned int		block;			/* Threshold block number within bank */
+	unsigned int		bank;			/* MCA bank the block belongs to */
+	unsigned int		cpu;			/* CPU which controls the MCA bank */
+	u32			address;		/* MSR address for the block */
+	u16			interrupt_enable;	/* Enable/ Disable APIC interrupt upon threshold error */
+	bool			interrupt_capable;	/* Specifies if interrupt is possible from the block */
+	u16			threshold_limit;	/* Value upon which threshold interrupt is generated */
+	struct kobject		kobj;			/* sysfs object */
+	struct list_head	miscj;			/* Add multiple threshold blocks within a bank to the list */
 };
 
 struct threshold_bank {
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 879c20f..f5b4b80 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -1,5 +1,5 @@
 /*
- *  (c) 2005-2015 Advanced Micro Devices, Inc.
+ *  (c) 2005-2016 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
@@ -202,10 +202,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 	return 1;
 };
 
-/*
- * Called via smp_call_function_single(), must be called with correct
- * cpu affinity.
- */
+/* Reprogram MCx_MISC MSR behind this threshold bank */
 static void threshold_restart_bank(void *_tr)
 {
 	struct thresh_restart *tr = _tr;
-- 
2.7.0