Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758170AbcCCP4I (ORCPT ); Thu, 3 Mar 2016 10:56:08 -0500 Received: from mail-bn1bon0062.outbound.protection.outlook.com ([157.56.111.62]:60128 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756104AbcCCPzK (ORCPT ); Thu, 3 Mar 2016 10:55:10 -0500 Authentication-Results: alien8.de; dkim=none (message not signed) header.d=none;alien8.de; dmarc=none action=none header.from=amd.com; From: Aravind Gopalakrishnan To: , , , , , , CC: , , , , , , , , , Subject: [PATCH V3 3/5] x86/mce/AMD: Fix logic to obtain block address Date: Thu, 3 Mar 2016 10:10:56 -0600 Message-ID: <1457021458-2522-4-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1457021458-2522-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1457021458-2522-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN1PR0701CA0022.namprd07.prod.outlook.com (25.162.96.32) To BY1PR12MB0421.namprd12.prod.outlook.com (25.162.146.30) X-MS-Office365-Filtering-Correlation-Id: 29e776db-211a-44d9-16ea-08d3437c2e34 X-Microsoft-Exchange-Diagnostics: 1;BY1PR12MB0421;2:C65hOi1anxRl0yHrkFEFi243z3JYRBGy0YCVnfrG2HVmteB+5tyXx4A0yis2P9xIBZ/FJojVHVzFRf2Om3OQf2b9iEZCyyx7uiPkJjfUmuNi/R5wKlxVkuxH2+vgzwxR2SBiIcYGnjIWD3avZvH2O3KE+/v67SiMJ3g0o++xAf9u56cDQvMM1drYDxznZblF;3:nbMZmWM/uvjFTQhk8KT8+46dxl4Bq63PIZ1ba2YJzMlXRYop/PKmgqIINeupHjowcrmaKGpgbff1MyAcj/MESni8gVDp5StriMG7m/VLg/NJ6oa0cAgcr7ZVXEEh0Pkf;25:BjCylZAENctk4XUJncPyH3rewOqfKgjKMhC3rcs6hucafw1NZnOMyA044tvHQQjAle4GDR3zSh2AB0FQxnkp1ldpNzFYIYR7tAawgmkQqRVDKO4rtGfY2GNbzFowNwUdxDlivT0eVFwAss2SHZ9F2faQD5x4e/VBM1mlx+jC7GhytdqQoUbeG5Ey3pZCpuJ2nvu2IvkHPbQuAhWYkA21dU60Ooyfgg58uYOEwma7QCHk6H7LfwosYtr/iKqPlsUsbdXFOlotHXX72iMn6IwaCTBqozqMjFBicZ9B6Fhc96DY6FLc5+0+3VXwjKXRWmHlAm/WUb0zN96EeTj/PADcfQ== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR12MB0421; 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Insted, it simply indicates the prescence of additional MSRs. Fixing the logic here to gather MSR address from MSR_AMD64_SMCA_MCx_MISC() for newer processors and we fall back to existing logic for older processors. Signed-off-by: Aravind Gopalakrishnan --- arch/x86/include/asm/mce.h | 4 ++ arch/x86/kernel/cpu/mcheck/mce_amd.c | 90 ++++++++++++++++++++++++------------ 2 files changed, 65 insertions(+), 29 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index cee098e..0681d0a 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -104,10 +104,14 @@ #define MCE_LOG_SIGNATURE "MACHINECHECK" /* 'SMCA': AMD64 Scalable MCA */ +#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003 #define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 #define MSR_AMD64_SMCA_MC0_IPID 0xc0002005 +#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a +#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) /* * This structure contains all data related to the MCE log. Also diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 7d495b6..879c20f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -305,6 +305,54 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) wrmsr(MSR_CU_DEF_ERR, low, high); } +static u32 get_block_address(u32 current_addr, u32 low, u32 high, + unsigned int bank, unsigned int block) +{ + u32 addr = 0, offset = 0; + + if (mce_flags.smca) { + if (!block) { + addr = MSR_AMD64_SMCA_MCx_MISC(bank); + } else { + /* + * For SMCA enabled processors, BLKPTR field + * of the first MISC register (MCx_MISC0) indicates + * presence of additional MISC register set (MISC1-4) + */ + u32 low, high; + + if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), + &low, &high) || + !(low & MCI_CONFIG_MCAX)) + goto nextaddr_out; + + if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), + &low, &high) && + (low & MASK_BLKPTR_LO)) + addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); + } + + goto nextaddr_out; + } + + /* Fall back to method we used for older processors */ + switch (block) { + case 0: + addr = MSR_IA32_MCx_MISC(bank); + break; + case 1: + offset = ((low & MASK_BLKPTR_LO) >> 21); + if (offset) + addr = MCG_XBLK_ADDR + offset; + break; + default: + addr = ++current_addr; + } + +nextaddr_out: + return addr; +} + static int prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, int offset, u32 misc_high) @@ -367,16 +415,10 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) for (bank = 0; bank < mca_cfg.banks; ++bank) { for (block = 0; block < NR_BLOCKS; ++block) { - if (block == 0) - address = MSR_IA32_MCx_MISC(bank); - else if (block == 1) { - address = (low & MASK_BLKPTR_LO) >> 21; - if (!address) - break; - - address += MCG_XBLK_ADDR; - } else - ++address; + address = get_block_address(address, low, high, + bank, block); + if (!address) + break; if (rdmsr_safe(address, &low, &high)) break; @@ -481,16 +523,10 @@ static void amd_threshold_interrupt(void) if (!(per_cpu(bank_map, cpu) & (1 << bank))) continue; for (block = 0; block < NR_BLOCKS; ++block) { - if (block == 0) { - address = MSR_IA32_MCx_MISC(bank); - } else if (block == 1) { - address = (low & MASK_BLKPTR_LO) >> 21; - if (!address) - break; - address += MCG_XBLK_ADDR; - } else { - ++address; - } + address = get_block_address(address, low, high, + bank, block); + if (!address) + break; if (rdmsr_safe(address, &low, &high)) break; @@ -710,16 +746,12 @@ static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, if (err) goto out_free; recurse: - if (!block) { - address = (low & MASK_BLKPTR_LO) >> 21; - if (!address) - return 0; - address += MCG_XBLK_ADDR; - } else { - ++address; - } + address = get_block_address(address, low, high, bank, ++block); + + if (!address) + return 0; - err = allocate_threshold_blocks(cpu, bank, ++block, address); + err = allocate_threshold_blocks(cpu, bank, block, address); if (err) goto out_free; -- 2.7.0