Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932267AbcCCQ2N (ORCPT ); Thu, 3 Mar 2016 11:28:13 -0500 Received: from mail-bl2nam02on0062.outbound.protection.outlook.com ([104.47.38.62]:3104 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751002AbcCCQ2L convert rfc822-to-8bit (ORCPT ); Thu, 3 Mar 2016 11:28:11 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Appana Durga Kedareswara Rao To: Vinod Koul CC: "dan.j.williams@intel.com" , Michal Simek , Soren Brinkmann , "moritz.fischer@ettus.com" , "laurent.pinchart@ideasonboard.com" , "luis@debethencourt.com" , Anirudha Sarangi , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine handling Thread-Topic: [PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine handling Thread-Index: AQHRcJ6gKAnZ7yxzD0uIWelTdyPqo59HXLGAgACVFBA= Date: Thu, 3 Mar 2016 16:28:01 +0000 Message-ID: References: <1456495434-11722-1-git-send-email-appanad@xilinx.com> <20160303153323.GN11154@localhost> In-Reply-To: <20160303153323.GN11154@localhost> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.229.5] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22168.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(979002)(6009001)(2980300002)(438002)(377454003)(24454002)(199003)(189002)(13464003)(47776003)(76176999)(2906002)(4326007)(5008740100001)(6806005)(97756001)(50466002)(54356999)(55846006)(50986999)(5250100002)(46406003)(81166005)(11100500001)(586003)(19580395003)(19580405001)(110136002)(106466001)(1096002)(92566002)(87936001)(5003600100002)(5004730100002)(6116002)(2950100001)(63266004)(102836003)(86362001)(2920100001)(106116001)(551934003)(23726003)(2900100001)(1220700001)(33656002)(3846002)(189998001)(107986001)(969003)(989001)(999001)(1009001)(1019001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT142;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:ovrnspm;A:1;MX:1;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 3906b583-0b96-46dd-f64f-08d34380ce40 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT142; X-Microsoft-Antispam-PRVS: <83ffb3a3670740869267b52e02e5f106@SN1NAM02HT142.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13018025)(5005006)(8121501046)(13015025)(13024025)(13017025)(13023025)(10201501046)(3002001);SRVR:SN1NAM02HT142;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT142; X-Forefront-PRVS: 0870212862 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2016 16:28:05.5078 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT142 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1367 Lines: 36 > -----Original Message----- > From: Vinod Koul [mailto:vinod.koul@intel.com] > Sent: Thursday, March 03, 2016 9:03 PM > To: Appana Durga Kedareswara Rao > Cc: dan.j.williams@intel.com; Michal Simek; Soren Brinkmann; Appana Durga > Kedareswara Rao; moritz.fischer@ettus.com; > laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha > Sarangi; dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine > handling > > On Fri, Feb 26, 2016 at 07:33:51PM +0530, Kedareswara rao Appana wrote: > > The current driver allows user to queue up multiple segments on to a > > single transaction descriptor. User will submit this single desc and > > in the issue_pending() we decode multiple segments and submit to SG HW > engine. > > We free up the allocated_desc when it is submitted to the HW. > > > > Existing code prevents the user to prepare multiple trasactions at > > same time as we are overwrite with the allocated_desc. > > > > The best utilization of HW SG engine would happen if we collate the > > pending list when we start dma this patch updates the same. > > Applied all. It is usually advisable to do cover letter using --cover-letter for multi > patch series Thanks ... Will fix next time onwards... Regards, Kedar. > > -- > ~Vinod