Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758114AbcCCRde (ORCPT ); Thu, 3 Mar 2016 12:33:34 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:63726 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752052AbcCCRdc (ORCPT ); Thu, 3 Mar 2016 12:33:32 -0500 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Russell King - ARM Linux , jason@lakedaemon.net, Neil Armstrong , Marc Zyngier , linux-kernel@vger.kernel.org, tglx@linutronix.de, Ma Haijun Subject: Re: [PATCH 02/17] irqchip: Add PLX Technology RPS IRQ Controller Date: Thu, 03 Mar 2016 18:32:52 +0100 Message-ID: <1592236.k0nfM7OxLV@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <20160303133649.GX19428@n2100.arm.linux.org.uk> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> <7673826.decBlDRz96@wuerfel> <20160303133649.GX19428@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:YMD8PIPuqr57LrIko7v9EP1sWjJpAYYzI4kc4797BKbdsqDGZTS MPbpAI8UXFh0+NhPBCW6f2baWPljei4oSIWEqkDNmMl+gUj6lcdBiwSMPpSTgV6PDEld5JX j5pb7DPm/zlk3UTa4+/jwwmdoxgJQOKzZUl5Ep4sbkyMplCc6BkkO2dxH2ihSkajy0SvqIw lRiZP+RRWR+JER4CEIjYw== X-UI-Out-Filterresults: notjunk:1;V01:K0:6ejHrw3/yKQ=:xRj9OmQEb5EHrrwUJa4A+g QRFV3mAeNsIosvyToJngQdyVc4QjewzVOFepLcRNIrhT6namRx89heEaFWMTSjRlOnrGDUT/D lVLWxkF+AidG6nOs3alIloVPgJ1lftPjQB2uZPsS8SJFlQARm5XdYyE2VfV+iZZcifC2MDT12 tpB5Iax16l72iPtnHrocuK8Zs/s+jsak+r1sHHFb5iGnoTlYfFH4YPSK6kCgskqggAV59KiIf pt/w/v5vW34xcOhIAPxGIPPMGM5mBBmb4BVrmIvwlM5VWL0YKQuow+k5XGnh6JAB897eT3WHo +bWI+bU9/Xi4cjyCUqXWkr+HLF4G0Ownw18lNoKsAG6RkgVwpEDd5KQhQfPoIUJV5dsk22eDY SxuNyeAvLkwWI9n4ev1pkPWr/JJkGcx5c3HqTufxT6huA66YLnEQpmeBxC2pALHCyjRUxrMVb Xc3aj/+qY8dYELtRMEwXgnr8rfN8/gg+NVLncuIB1LdwlVd5tcsPqR8CQRacIdQjMT26ed2ld KQX5up004Fi5TQzOW5FHjQiq0kRjwx/BxWKoK0Zg7bF5sIdKoPeTWMHr3gMAjL/yqvSOpvDYR lQLEYO5MvFkMCKSIM9EOdb+nmYop0oxZ8BE1ov6owBTNa/ioJCVB1WQXLGhPhDBlTFeAsAolS fNj6Fl8wC/LXsAf1aDCMzl3xaKNErb70ibiPBy897GboYdPBfLxuRenr2VKsuG+76FtUt0NXR 39+DTWsmRTTNayRn Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1653 Lines: 36 On Thursday 03 March 2016 13:36:49 Russell King - ARM Linux wrote: > On Thu, Mar 03, 2016 at 02:08:19PM +0100, Arnd Bergmann wrote: > > On Thursday 03 March 2016 13:01:13 Marc Zyngier wrote: > > > > +/* Routines to acknowledge, disable and enable interrupts */ > > > > +static void rps_mask_irq(struct irq_data *d) > > > > +{ > > > > + u32 mask = BIT(d->hwirq); > > > > + > > > > + iowrite32(mask, rps_data.base + RPS_MASK); > > > > > > I do question the use of iowrite32 here (and its ioread32 pendent > > > anywhere else), as it actually translates in a writel, which contains a > > > memory barrier. Do you have any case that requires the use of such a > > > barrier? if not, consider switching to relaxed accessors (which are the > > > > > > > I really ask everyone to do the opposite: we have seen several drivers > > blindlessly using the relaxed accessors and actually introducing bugs > > that way, so I'd rather see the readl/writel ones used by default. > > I actually agree with Marc - we have far too many drivers using the > barriered IO accessors, which are really very expensive on 32-bit > ARM. > > For most ARM systems, the rules are quite simple: a write which causes > DMA memory to be accessed by the device must be using the barriered > IO accessor, and a read from a DMA status register must be too. > Everything else need not be. Barriered IO accessors are only about > access ordering. My main worry is really about code getting copied from drivers that are fine with just relaxed accessors into other drivers by developers that have never heard about the difference and just want to follow best practices. Arnd