Date: Thu, 3 Mar 2016 19:45:48 +0100
From: Borislav Petkov <bp@alien8.de>
To: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: tony.luck@intel.com, hpa@zytor.com, mingo@redhat.com, tglx@linutronix.de,
        dougthompson@xmission.com, mchehab@osg.samsung.com, x86@kernel.org,
        linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
        ashok.raj@intel.com, gong.chen@linux.intel.com, len.brown@intel.com,
        peterz@infradead.org, ak@linux.intel.com,
        alexander.shishkin@linux.intel.com, Yazen.Ghannam@amd.com
Subject: Re: [PATCH V3 0/5] Updates to EDAC and AMD MCE driver
Message-ID: <20160303184548.GF24621@pd.tnic>
References: <1457021458-2522-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
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On Thu, Mar 03, 2016 at 10:10:53AM -0600, Aravind Gopalakrishnan wrote:
> This patchset mainly provides necessary EDAC bits to decode errors
> occuring on Scalable MCA enabled processors and also updates AMD MCE
> driver to program the correct MCx_MISC register address for upcoming
> processors.
> 
> Patches 1, 2 and 3 are for upcoming processor.
> 
> Patches 4 and 5 are either fixing or adding comments to help in
> understanding the code and do not introduce any functional changes.
> 
> Patch 1: Move MSR definition to mce.h
> Patch 2: Updates to EDAC driver to decode the new error signatures
> Patch 3: Fix logic to obtain correct block address
> Patch 4: Fix deferred error comment
> Patch 5: Add comments to amd_nb.h to describe threshold_block structure
> 
> Note 1: Introduced new patch for moving MCx_CONFIG MSR to mce.h
> Note 2: The enums, amd_hwids[], and string arrays amd_core_mcablock_names[],
> 	amd_df_mcablock_names[] are placed in arch/x86 as there are
> 	follow-up patches which use them here.
> 
> Changes from V1: (per Boris suggestions)
>   - Simplify error decoding routines
>   - Move headers to mce.h
>   - Rename enumerations and struct members (to be more descriptive)
>   - Drop gerund usage
>   - Remove comments that are spelling out the code
> 
> Changes from V2: (per Boris suggestions)
>   - Incorporated all changes as suggested by Boris from here-
>     - http://marc.info/?l=linux-kernel&m=145691594921586&w=2
>     - http://marc.info/?l=linux-kernel&m=145691606221610&w=2
>     - http://marc.info/?l=linux-kernel&m=145691610421627&w=2
>   - No functional change is introduced
> 
> Aravind Gopalakrishnan (5):
>   x86/mce: Move MCx_CONFIG MSR definition
>   EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
>   x86/mce/AMD: Fix logic to obtain block address
>   x86/mce: Clarify comments regarding deferred error
>   x86/mce/AMD: Add comments for easier understanding
> 
>  arch/x86/include/asm/amd_nb.h        |  18 +-
>  arch/x86/include/asm/mce.h           |  69 +++++++-
>  arch/x86/include/asm/msr-index.h     |   4 -
>  arch/x86/kernel/cpu/mcheck/mce_amd.c | 127 +++++++++----
>  drivers/edac/mce_amd.c               | 334 ++++++++++++++++++++++++++++++++++-
>  5 files changed, 501 insertions(+), 51 deletions(-)

Applied, minor stuff corrected and pushed out to

http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras

so that the 0day bot can chew on them a little.

Thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.