Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932265AbcCCTvD (ORCPT ); Thu, 3 Mar 2016 14:51:03 -0500 Received: from mail-pf0-f176.google.com ([209.85.192.176]:35033 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754700AbcCCTu6 (ORCPT ); Thu, 3 Mar 2016 14:50:58 -0500 From: Stephane Eranian To: linux-kernel@vger.kernel.org Cc: acme@redhat.com, peterz@infradead.org, mingo@elte.hu, ak@linux.intel.com, kan.liang@intel.com, jolsa@redhat.com, namhyung@kernel.org, adrian.hunter@intel.com Subject: [PATCH 1/3] perf/x86/intel: add definition for PT PMI bit Date: Thu, 3 Mar 2016 20:50:40 +0100 Message-Id: <1457034642-21837-2-git-send-email-eranian@google.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457034642-21837-1-git-send-email-eranian@google.com> References: <1457034642-21837-1-git-send-email-eranian@google.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 729 Lines: 22 This patch adds a definition for GLOBAL_OVFL_STATUS bit 55 which is used with the Processor Trace (PT) feature. Signed-off-by: Stephane Eranian --- arch/x86/include/asm/perf_event.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 7bcb861..5a2ed3e 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -165,6 +165,7 @@ struct x86_pmu_capability { #define GLOBAL_STATUS_ASIF BIT_ULL(60) #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59) #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58) +#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55) /* * IBS cpuid feature detection -- 2.5.0