Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760283AbcCDVrp (ORCPT ); Fri, 4 Mar 2016 16:47:45 -0500 Received: from mail-vk0-f45.google.com ([209.85.213.45]:36030 "EHLO mail-vk0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759544AbcCDVrm (ORCPT ); Fri, 4 Mar 2016 16:47:42 -0500 MIME-Version: 1.0 In-Reply-To: <1457108379-20794-1-git-send-email-thierry.reding@gmail.com> References: <1457108379-20794-1-git-send-email-thierry.reding@gmail.com> Date: Fri, 4 Mar 2016 13:47:41 -0800 X-Google-Sender-Auth: cJKxj8IWvWyYVh0qzjJop1kr_hw Message-ID: Subject: Re: [PATCH v10 1/9] dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding From: Andrew Bresticker To: Thierry Reding Cc: Kishon Vijay Abraham I , Linus Walleij , Stephen Warren , Alexandre Courbot , "linux-tegra@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 569 Lines: 13 > +Required properties: > +-------------------- > +- compatible: Must be: > + - Tegra124: "nvidia,tegra124-xusb-padctl" > + - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" > +- reg: Physical base address and length of the controller's registers. > +- resets: Must contain an entry for each entry in reset-names. > +- reset-names: Must include the following entries: > + - "padctl" Also... there's a padctl interrupt that'll be necessary for LP0 suspend/resume and runtime power-gating of the xHC. We should probably include that here too.