Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760544AbcCDXwT (ORCPT ); Fri, 4 Mar 2016 18:52:19 -0500 Received: from mail-lb0-f174.google.com ([209.85.217.174]:35207 "EHLO mail-lb0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760366AbcCDXwR (ORCPT ); Fri, 4 Mar 2016 18:52:17 -0500 Subject: Re: [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset() To: Douglas Anderson , johnyoun@synopsys.com, balbi@kernel.org, Heiko Stuebner References: <1457115786-11370-1-git-send-email-dianders@chromium.org> Cc: linux@mniewoehner.de, caesar.upstream@gmail.com, huangtao@rock-chips.com, repk@triplefau.lt, stefan.wahren@i2se.com, Julius Werner , gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org From: Sergei Shtylyov Organization: Cogent Embedded Message-ID: <56DA1FAB.3040200@cogentembedded.com> Date: Sat, 5 Mar 2016 02:52:11 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: <1457115786-11370-1-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1278 Lines: 38 Hello. On 03/04/2016 09:23 PM, Douglas Anderson wrote: > From testing and trying to make sense of the documentation, it appears > that a 10 ms delay is needed after resetting the core to make sure that > everything is stable and consistent. Let's add it. > > In my testing (on rk3288) this allows us to revert commit > 192cb07f7928 ("usb: dwc2: Fix probe problem on bcm2835"). Though I > could never reproduce the problems on my board, this might also allow us > to revert commit bd84f4ae9986 ("usb: dwc2: Add extra delay when forcing > dr_mode"). > > Signed-off-by: Douglas Anderson > --- > drivers/usb/dwc2/core.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c > index 5e5a0f135b5a..8710b2d3e770 100644 > --- a/drivers/usb/dwc2/core.c > +++ b/drivers/usb/dwc2/core.c > @@ -277,6 +277,26 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg) > } > } while (!(greset & GRSTCTL_AHBIDLE)); > > + /* > + * Sleep for 10-15 ms after the reset to let it finish. > + * > + * It's been confirmed on at least one version of the controller > + * that this is a requirement that this is a requirement in order for Saying it once is enough. :-) [...] MBR, Sergei