Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760267AbcCECXI (ORCPT ); Fri, 4 Mar 2016 21:23:08 -0500 Received: from smtprelay.synopsys.com ([198.182.60.111]:45831 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759575AbcCECXG (ORCPT ); Fri, 4 Mar 2016 21:23:06 -0500 Subject: Re: [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset() To: Douglas Anderson , "John.Youn@synopsys.com" , "balbi@kernel.org" , "Heiko Stuebner" References: <1457115786-11370-1-git-send-email-dianders@chromium.org> CC: "linux@mniewoehner.de" , "caesar.upstream@gmail.com" , "huangtao@rock-chips.com" , "repk@triplefau.lt" , "stefan.wahren@i2se.com" , Julius Werner , "gregkh@linuxfoundation.org" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" From: John Youn Message-ID: <56DA4305.7010300@synopsys.com> Date: Fri, 4 Mar 2016 18:23:01 -0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1457115786-11370-1-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.10.161.122] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2069 Lines: 60 On 3/4/2016 10:23 AM, Douglas Anderson wrote: > From testing and trying to make sense of the documentation, it appears > that a 10 ms delay is needed after resetting the core to make sure that > everything is stable and consistent. Let's add it. > > In my testing (on rk3288) this allows us to revert commit > 192cb07f7928 ("usb: dwc2: Fix probe problem on bcm2835"). Though I > could never reproduce the problems on my board, this might also allow us > to revert commit bd84f4ae9986 ("usb: dwc2: Add extra delay when forcing > dr_mode"). > > Signed-off-by: Douglas Anderson > --- > drivers/usb/dwc2/core.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c > index 5e5a0f135b5a..8710b2d3e770 100644 > --- a/drivers/usb/dwc2/core.c > +++ b/drivers/usb/dwc2/core.c > @@ -277,6 +277,26 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg) > } > } while (!(greset & GRSTCTL_AHBIDLE)); > > + /* > + * Sleep for 10-15 ms after the reset to let it finish. > + * > + * It's been confirmed on at least one version of the controller > + * that this is a requirement that this is a requirement in order for > + * everything to settle. Specifically if you: > + * - change GNPTXFSIZ or HPTXFSIZ before the reset > + * - do the reset > + * - read GNPTXFSIZ or HPTXFSIZ in a loop > + * ...you'll find that it takes almost exactly 10 ms for the registers > + * to return to their reset defaults. > + * > + * Note that it's possible that this 10 ms is the time referred to > + * in "Host Initialization" where it says to "Wait at least 10 ms for > + * the reset process to complete". In "Device Initialization" there > + * is also talk of a reset lasting 10 ms. That may be the source of > + * this delay. > + */ > + usleep_range(10000, 15000); > + > return 0; > } > > Hi Doug, Thanks for tracking this down. Caesar, Could you test these two commits on your rk3066 platform? And also see if it works after reverting bd84f4ae9986? Thanks, John