Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751002AbcCEWpw (ORCPT ); Sat, 5 Mar 2016 17:45:52 -0500 Received: from rev33.vpn.fdn.fr ([80.67.179.33]:51491 "EHLO outils.crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751026AbcCEWpj (ORCPT ); Sat, 5 Mar 2016 17:45:39 -0500 From: Paul Cercueil To: Alexandre Belloni Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Ralf Baechle , Alessandro Zummo , Paul Cercueil , Paul Burton , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: [PATCH 2/5] Documentation: dt: Add binding info for jz4740-rtc driver Date: Sat, 5 Mar 2016 23:38:48 +0100 Message-Id: <1457217531-26064-2-git-send-email-paul@crapouillou.net> In-Reply-To: <1457217531-26064-1-git-send-email-paul@crapouillou.net> References: <1457217531-26064-1-git-send-email-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1628 Lines: 52 Signed-off-by: Paul Cercueil --- .../devicetree/bindings/rtc/ingenic,jz4740-rtc.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt new file mode 100644 index 0000000..71e4ad0 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt @@ -0,0 +1,38 @@ +JZ4740 and similar SoCs real-time clock driver + +Required properties: + +- compatible: One of: + - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC + - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC +- reg: Address range of rtc register set +- interrupts: IRQ number for the alarm interrupt +- interrupt-parent: phandle of the interrupt controller +- clocks: phandle to the "rtc" clock +- clock-names: must be "rtc" + +Optional properties: +- system-power-controller: To use this component as the + system power controller +- reset-pin-assert-time: Reset pin low-level assertion time + after wakeup (default 60ms; range 0-125ms if RTC clock at + 32 kHz) +- min-wakeup-pin-assert-time: Minimum wakeup pin assertion time + (default 100ms; range 0-2s if RTC clock at 32 kHz) + +Example: + +rtc@10003000 { + compatible = "ingenic,jz4740-rtc"; + reg = <0x10003000 0x3F>; + + interrupt-parent = <&intc>; + interrupts = <32>; + + clocks = <&rtc_clock>; + clock-names = "rtc"; + + system-power-controller; + reset-pin-assert-time = <60>; + min-wakeup-pin-assert-time = <100>; +}; -- 2.7.0