Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752088AbcCGCrr (ORCPT ); Sun, 6 Mar 2016 21:47:47 -0500 Received: from mail-io0-f196.google.com ([209.85.223.196]:36824 "EHLO mail-io0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751641AbcCGCrl (ORCPT ); Sun, 6 Mar 2016 21:47:41 -0500 MIME-Version: 1.0 In-Reply-To: <1457192586-25596-3-git-send-email-vishnupatekar0510@gmail.com> References: <1457192586-25596-1-git-send-email-vishnupatekar0510@gmail.com> <1457192586-25596-3-git-send-email-vishnupatekar0510@gmail.com> From: Julian Calaby Date: Mon, 7 Mar 2016 13:47:19 +1100 Message-ID: Subject: Re: [linux-sunxi] [PATCH v3 02/13] clk: sunxi: add ahb1 clock for A83T To: Vishnu Patekar Cc: Rob Herring , Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Maxime Ripard , Russell King , Emilio Lopez , Jens Kuske , Hans De Goede , Chen-Yu Tsai , devicetree , "Mailing List, Arm" , "linux-kernel@vger.kernel.org" , linux-sunxi , linux-gpio@vger.kernel.org, Linus Walleij , Michael Turquette , sboyd@codeaurora.org, Reinder de Haan , linux-clk@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5242 Lines: 146 Hi Vishnu, On Sun, Mar 6, 2016 at 2:42 AM, Vishnu Patekar wrote: > AHB1 on A83T is similar to ahb1 on A31, except parents are different. > clock index 0b1x is PLL6. > > Signed-off-by: Vishnu Patekar > Acked-by: Chen-Yu Tsai > Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/clk-sunxi.c | 76 +++++++++++++++++++++++ > 2 files changed, 77 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index c09f59b..2ee7841 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -29,6 +29,7 @@ Required properties: > "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 > "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 > "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 > + "allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T > "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 > "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 > "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c > index 99f60ef..0ae1f09 100644 > --- a/drivers/clk/sunxi/clk-sunxi.c > +++ b/drivers/clk/sunxi/clk-sunxi.c > @@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req) > req->rate >>= req->p; > } > > +#define SUN8I_A83T_AHB1_PARENT_PLL6 2 > +/** > + * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB > + * AHB rate is calculated as follows > + * rate = parent_rate >> p > + * > + * if parent is pll6, then > + * parent_rate = pll6 rate / (m + 1) > + */ > + > +static void sun8i_a83t_get_ahb1_factors(struct factors_request *req) > +{ > + u8 div, calcp, calcm = 1; > + > + /* > + * clock can only divide, so we will never be able to achieve > + * frequencies higher than the parent frequency > + */ > + if (req->parent_rate && req->rate > req->parent_rate) > + req->rate = req->parent_rate; > + > + div = DIV_ROUND_UP(req->parent_rate, req->rate); > + > + /* calculate pre-divider if parent is pll6 */ > + if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) { > + if (div < 4) > + calcp = 0; > + else if (div / 2 < 4) > + calcp = 1; > + else if (div / 4 < 4) > + calcp = 2; > + else > + calcp = 3; > + > + calcm = DIV_ROUND_UP(div, 1 << calcp); > + } else { > + calcp = __roundup_pow_of_two(div); > + calcp = calcp > 3 ? 3 : calcp; > +} You could do with a tab here. > + > + req->rate = (req->parent_rate / calcm) >> calcp; > + req->p = calcp; > + req->m = calcm - 1; > +} > + > +/** > +* sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and > +* parent index > +*/ > +static void sun8i_a83t_ahb1_recalc(struct factors_request *req) > +{ > + req->rate = req->parent_rate; > + > +/* apply pre-divider first if parent is pll6 */ > + if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6) > + req->rate /= req->m + 1; > + > + /* clk divider */ > + req->rate >>= req->p; > +} > + > /** > * sun4i_get_apb1_factors() - calculates m, p factors for APB1 > * APB1 rate is calculated as follows > @@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data __initconst = { > .recalc = sun6i_ahb1_recalc, > }; > > +static const struct factors_data sun8i_a83t_ahb1_data __initconst = { > + .mux = 12, > + .muxmask = BIT(1) | BIT(0), > + .table = &sun6i_ahb1_config, > + .getter = sun8i_a83t_get_ahb1_factors, > + .recalc = sun8i_a83t_ahb1_recalc, > +}; > + > static const struct factors_data sun4i_apb1_data __initconst = { > .mux = 24, > .muxmask = BIT(1) | BIT(0), > @@ -627,6 +696,13 @@ static void __init sun6i_ahb1_clk_setup(struct device_node *node) > CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", > sun6i_ahb1_clk_setup); > > +static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node) > +{ > + sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data); > +} > +CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk", > + sun8i_a83t_ahb1_clk_setup); > + > static void __init sun4i_apb1_clk_setup(struct device_node *node) > { > sunxi_factors_clk_setup(node, &sun4i_apb1_data); > -- > 1.9.1 > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/