Date: Mon, 7 Mar 2016 09:38:42 +0100
From: Thierry Reding <thierry.reding@gmail.com>
To: Wei Ni <wni@nvidia.com>
Cc: rui.zhang@intel.com, MLongnecker@nvidia.com, mikko.perttunen@kapsi.fi,
        swarren@wwwdotorg.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] thermal: tegra_soctherm: fix sign bit of temperature
Message-ID: <20160307083842.GC31189@ulmo.nvidia.com>
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On Mon, Feb 29, 2016 at 05:51:20PM +0800, Wei Ni wrote:
> The sign bit of temperature readback is bit 0, not bit 1.
> Change to BIT(0) to fix it.
>=20
> Signed-off-by: Wei Ni <wni@nvidia.com>
> ---
>  drivers/thermal/tegra_soctherm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soc=
therm.c
> index 74ea5765938b..136975220c92 100644
> --- a/drivers/thermal/tegra_soctherm.c
> +++ b/drivers/thermal/tegra_soctherm.c
> @@ -57,7 +57,7 @@
>  #define READBACK_VALUE_MASK			0xff00
>  #define READBACK_VALUE_SHIFT			8
>  #define READBACK_ADD_HALF			BIT(7)
> -#define READBACK_NEGATE				BIT(1)
> +#define READBACK_NEGATE				BIT(0)

I haven't found this documented anywhere. The register documentation
indicates that the SOC_THERM_TSENSOR_TEMP1 and SOC_THERM_TSENSOR_TEMP2
registers are in some kind of "temp readback format", but I can't find
any specification of that format. Can you point me at the source for
this information and file an internal bug report so that we can get
the documentation updated?

Thierry

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