Date: Mon, 7 Mar 2016 21:30:24 +0100
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Vinod Koul <vinod.koul@intel.com>, Dan Williams <dan.j.williams@intel.com>,
        dmaengine@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
        linux-sunxi@googlegroups.com,
        Emilio =?iso-8859-1?Q?L=F3pez?= <emilio@elopez.com.ar>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dma: sun4i: expose block size and wait cycle
 configuration to DMA users
Message-ID: <20160307203024.GD8418@lukather>
References: <1457344771-12946-1-git-send-email-boris.brezillon@free-electrons.com>
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 <20160307160857.577bb04d@bbrezillon>
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On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
> Hi Vinod,
>=20
> On Mon, 7 Mar 2016 20:24:29 +0530
> Vinod Koul <vinod.koul@intel.com> wrote:
>=20
> > On Mon, Mar 07, 2016 at 10:59:31AM +0100, Boris Brezillon wrote:
> > > +/* Dedicated DMA parameter register layout */
> > > +#define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n)	(((n) - 1) << 24)
> > > +#define SUN4I_DDMA_PARA_DST_WAIT_CYCLES(n)	(((n) - 1) << 16)
> > > +#define SUN4I_DDMA_PARA_SRC_DATA_BLK_SIZE(n)	(((n) - 1) << 8)
> > > +#define SUN4I_DDMA_PARA_SRC_WAIT_CYCLES(n)	(((n) - 1) << 0)
> > > +
> > > +/**
> > > + * struct sun4i_dma_chan_config - DMA channel config
> > > + *
> > > + * @para: contains information about block size and time before chec=
king
> > > + *	  DRQ line. This is device specific and only applicable to dedica=
ted
> > > + *	  DMA channels
> >=20
> > What information, can you elobrate.. And why can't you use existing
> > dma_slave_config for this?
>=20
> Block size is related to the device FIFO size. I guess it allows the
> DMA channel to launch a transfer of X bytes without having to check the
> DRQ line (the line telling the DMA engine it can transfer more data
> to/from the device). The wait cycles information is apparently related
> to the number of clks the engine should wait before polling/checking
> the DRQ line status between each block transfer. I'm not sure what it
> saves to put WAIT_CYCLES() to something !=3D 1, but in their BSP,
> Allwinner tweak that depending on the device.
>=20
> Note that I'd be happy if the above configuration could go into the
> generic dma_slave_config struct. This way we could avoid per-engine
> specific APIs.

And I'd really like to avoid that too. That will avoid to cripple the
consumer drivers that might be using any of the two.

Thanks!
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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