Date: Tue, 8 Mar 2016 15:29:04 +0530
From: Vinod Koul <vinod.koul@intel.com>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>,
        Dan Williams <dan.j.williams@intel.com>, dmaengine@vger.kernel.org,
        Chen-Yu Tsai <wens@csie.org>, linux-sunxi@googlegroups.com,
        Emilio =?iso-8859-1?Q?L=F3pez?= <emilio@elopez.com.ar>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dma: sun4i: expose block size and wait cycle
 configuration to DMA users
Message-ID: <20160308095904.GM11154@localhost>
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 <20160307160857.577bb04d@bbrezillon>
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On Tue, Mar 08, 2016 at 08:51:31AM +0100, Maxime Ripard wrote:
> > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > + *
> > > > > > + * @para: contains information about block size and time befor=
e checking
> > > > > > + *	  DRQ line. This is device specific and only applicable to =
dedicated
> > > > > > + *	  DMA channels
> > > > >=20
> > > > > What information, can you elobrate.. And why can't you use existi=
ng
> > > > > dma_slave_config for this?
> > > >=20
> > > > Block size is related to the device FIFO size. I guess it allows the
> > > > DMA channel to launch a transfer of X bytes without having to check=
 the
> > > > DRQ line (the line telling the DMA engine it can transfer more data
> > > > to/from the device). The wait cycles information is apparently rela=
ted
> > > > to the number of clks the engine should wait before polling/checking
> > > > the DRQ line status between each block transfer. I'm not sure what =
it
> > > > saves to put WAIT_CYCLES() to something !=3D 1, but in their BSP,
> > > > Allwinner tweak that depending on the device.
> >=20
> > we already have block size aka src/dst_maxburst, why not use that one.
>=20
> I'm not sure it's really the same thing. The DMA controller also has a
> burst parameter, that is either 1 byte or 8 bytes, and ends up being
> different from this one.

Nope that is buswidth. maxburst is words which cna be sent to device FIFO.
>=20
> > Why does dmaengine need to wait? Can you explain that
>=20
> We have no idea, we thought you might have one :)

Well that is hardware dependent. From DMAengine API usage we dont ahve to
wait at all. We should submit next descriptor as soon as possible.

> It doesn't really makes sense to us, but it does have a significant
> impact on the throughput.

--=20
~Vinod

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