Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932900AbcCHK7m (ORCPT ); Tue, 8 Mar 2016 05:59:42 -0500 Received: from mail-pa0-f41.google.com ([209.85.220.41]:35530 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932159AbcCHK7d (ORCPT ); Tue, 8 Mar 2016 05:59:33 -0500 Subject: Re: [PATCH v5 6/6] rockchip: power-domain: Modify power domain driver for rk3399 To: Elaine Zhang , wxt@rock-chips.com References: <1456992233-25164-1-git-send-email-zhangqing@rock-chips.com> <1456992591-25383-1-git-send-email-zhangqing@rock-chips.com> Cc: heiko@sntech.de, khilman@baylibre.com, huangtao@rock-chips.com, xxx@rock-chips.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, zyw@rock-chips.com, jay.xu@rock-chips.com, linux-arm-kernel@lists.infradead.org From: Caesar Wang Message-ID: <56DEB08E.5060805@gmail.com> Date: Tue, 8 Mar 2016 18:59:26 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <1456992591-25383-1-git-send-email-zhangqing@rock-chips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3875 Lines: 112 在 2016年03月03日 16:09, Elaine Zhang 写道: > This driver is modified to support RK3399 SoC. > > Signed-off-by: Elaine Zhang Reviewed-by: Caesar Wang > --- > drivers/soc/rockchip/pm_domains.c | 55 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 1777e8e..8cdd877 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > > struct rockchip_domain_info { > int pwr_mask; > @@ -79,6 +80,9 @@ struct rockchip_pmu { > #define DOMAIN_RK3368(pwr, status, req) \ > DOMAIN(pwr, status, req, (req) + 16, req) > > +#define DOMAIN_RK3399(pwr, status, req) \ > + DOMAIN(pwr, status, req, req, req) > + > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > struct rockchip_pmu *pmu = pd->pmu; > @@ -535,6 +539,36 @@ static const struct rockchip_domain_info rk3368_pm_domains[] = { > [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2), > }; > > +static const struct rockchip_domain_info rk3399_pm_domains[] = { > + [RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1), > + [RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1), > + [RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15), > + [RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16), > + [RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2), > + [RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14), > + [RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17), > + [RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3), > + [RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4), > + [RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5), > + [RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6), > + [RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1), > + [RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7), > + [RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8), > + [RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9), > + [RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10), > + [RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11), > + [RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23), > + [RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24), > + [RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12), > + [RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22), > + [RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27), > + [RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29), > +}; > + > static const struct rockchip_pmu_info rk3288_pmu = { > .pwr_offset = 0x08, > .status_offset = 0x0c, > @@ -569,6 +603,23 @@ static const struct rockchip_pmu_info rk3368_pmu = { > .domain_info = rk3368_pm_domains, > }; > > +static const struct rockchip_pmu_info rk3399_pmu = { > + .pwr_offset = 0x14, > + .status_offset = 0x18, > + .req_offset = 0x60, > + .idle_offset = 0x64, > + .ack_offset = 0x68, > + > + .core_pwrcnt_offset = 0x9c, > + .gpu_pwrcnt_offset = 0xa4, > + > + .core_power_transition_time = 24, > + .gpu_power_transition_time = 24, > + > + .num_domains = ARRAY_SIZE(rk3399_pm_domains), > + .domain_info = rk3399_pm_domains, > +}; > + > static const struct of_device_id rockchip_pm_domain_dt_match[] = { > { > .compatible = "rockchip,rk3288-power-controller", > @@ -578,6 +629,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { > .compatible = "rockchip,rk3368-power-controller", > .data = (void *)&rk3368_pmu, > }, > + { > + .compatible = "rockchip,rk3399-power-controller", > + .data = (void *)&rk3399_pmu, > + }, > { /* sentinel */ }, > }; > -- Thanks, Caesar