Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932240AbcCHPVS (ORCPT ); Tue, 8 Mar 2016 10:21:18 -0500 Received: from down.free-electrons.com ([37.187.137.238]:46391 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751359AbcCHPVD (ORCPT ); Tue, 8 Mar 2016 10:21:03 -0500 Date: Tue, 8 Mar 2016 16:20:40 +0100 From: Boris Brezillon To: Thomas Petazzoni Cc: David Woodhouse , Brian Norris , linux-mtd@lists.infradead.org, Chen-Yu Tsai , linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Maxime Ripard , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 02/16] mtd: nand: sunxi: fix clk rate calculation Message-ID: <20160308162040.7b659486@bbrezillon> In-Reply-To: <20160308155803.1b0263eb@free-electrons.com> References: <1457367513-26069-1-git-send-email-boris.brezillon@free-electrons.com> <1457367513-26069-3-git-send-email-boris.brezillon@free-electrons.com> <20160308155803.1b0263eb@free-electrons.com> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.27; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1615 Lines: 42 On Tue, 8 Mar 2016 15:58:03 +0100 Thomas Petazzoni wrote: > Boris, > > On Mon, 7 Mar 2016 17:18:19 +0100, Boris Brezillon wrote: > > Unlike what is specified in the Allwinner datasheets, the NAND clock rate > > is not equal to 2/T but 1/T. Fix the clock rate selection accordingly. > > > > Signed-off-by: Boris Brezillon > > --- > > drivers/mtd/nand/sunxi_nand.c | 8 +------- > > 1 file changed, 1 insertion(+), 7 deletions(-) > > > > diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c > > index 4d01e65..ab66d8d 100644 > > --- a/drivers/mtd/nand/sunxi_nand.c > > +++ b/drivers/mtd/nand/sunxi_nand.c > > @@ -1208,13 +1208,7 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, > > /* Convert min_clk_period from picoseconds to nanoseconds */ > > min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); > > > > - /* > > - * Convert min_clk_period into a clk frequency, then get the > > - * appropriate rate for the NAND controller IP given this formula > > - * (specified in the datasheet): > > - * nand clk_rate = 2 * min_clk_rate > > - */ > > When some HW works in a way that is *NOT* the one specified in the > datasheet, I think you should rather add *more* comments about this > aspect, rather than removing existing comments. Fair enough (but you know how much I like documenting my code ;)). I'll add a comment explaining why it differs from the datasheet description :P. -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com