Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933357AbcCIQuf (ORCPT ); Wed, 9 Mar 2016 11:50:35 -0500 Received: from gloria.sntech.de ([95.129.55.99]:43176 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753598AbcCIQu1 convert rfc822-to-8bit (ORCPT ); Wed, 9 Mar 2016 11:50:27 -0500 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Xing Zheng Cc: linux-rockchip@lists.infradead.org, huangtao@rock-chips.com, jay.xu@rock-chips.com, elaine.zhang@rock-chips.com, dianders@chromium.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/7] clk: rockchip: add more mux parameters for new pll sources Date: Wed, 09 Mar 2016 17:50:17 +0100 Message-ID: <6921896.5phntn5YJn@diego> User-Agent: KMail/4.14.10 (Linux/4.2.0-1-amd64; KDE/4.14.14; x86_64; ; ) In-Reply-To: <1457491027-30936-4-git-send-email-zhengxing@rock-chips.com> References: <1457491027-30936-1-git-send-email-zhengxing@rock-chips.com> <1457491027-30936-4-git-send-email-zhengxing@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 568 Lines: 16 Am Mittwoch, 9. M?rz 2016, 10:37:03 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. > > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. > > Signed-off-by: Xing Zheng applied to my clk-branch for v4.7, with an adapted subject of "clk: rockchip: allow varying mux parameters for cpuclk pll-sources" Thanks Heiko