Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934842AbcCJCSy (ORCPT ); Wed, 9 Mar 2016 21:18:54 -0500 Received: from mail.kmu-office.ch ([178.209.48.109]:37465 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752486AbcCJCR0 (ORCPT ); Wed, 9 Mar 2016 21:17:26 -0500 From: Stefan Agner To: shawnguo@kernel.org, mturquette@baylibre.com, sboyd@codeaurora.org Cc: kernel@pengutronix.de, sergeimir@emcraft.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Stefan Agner Subject: [PATCH 17/18] Documentation: dt: add Vybrid DDR memory controller bindings Date: Wed, 9 Mar 2016 18:16:58 -0800 Message-Id: <1457576219-7971-18-git-send-email-stefan@agner.ch> X-Mailer: git-send-email 2.7.2 In-Reply-To: <1457576219-7971-1-git-send-email-stefan@agner.ch> References: <1457576219-7971-1-git-send-email-stefan@agner.ch> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1524 Lines: 41 Add device-tree bindings of Vybrids LPDDR2/DDR3 SDRAM Memory Controller. Access to the device is required to put the memory into self-refresh mode. Signed-off-by: Stefan Agner --- .../bindings/arm/freescale/fsl,vf610-ddrmc.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt new file mode 100644 index 0000000..56a71d6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt @@ -0,0 +1,23 @@ +Freescale Vybrid LPDDR2/DDR3 SDRAM Memory Controller + +The memory controller supports high performance applications for 16-bit or +8-bit DDR2, or LPDDR SDRAM memories. + +Required properties: +- compatible: "fsl,vf610-ddrmc" +- reg: the register range of the DDRMC registers +- clocks: DDRMC main clock to clock memory and access registers. +- clock-names: Must contain "ddrc", matching entry in the clocks property. +- fsl,has-cke-reset-pulls: + States whether pull-down/up are populated on DDR CKE/RESET + signals to allow using DDR self-refresh modes (see Vybrid + Hardware Development Guide for details). + +Example: + ddrmc: ddrmc@400ae000 { + compatible = "fsl,vf610-ddrmc"; + reg = <0x400ae000 0x1000>; + clocks = <&clks VF610_CLK_DDRMC>; + clock-names = "ddrc"; + fsl,has-cke-reset-pulls; + } -- 2.7.2